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VSC7440 Datasheet(PDF) 350 Page - Microsemi Corporation

Part # VSC7440
Description  L2/L3 Enterprise Gigabit Ethernet Switch with 10 Gbps Links
PDF  444 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC7440 Datasheet(HTML) 350 Page - Microsemi Corporation

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VCore-III System and CPU Interfaces
VMDS-10492 VSC7440 Datasheet Revision 4.2
333
Figure 113 •
Injection Status Word Encoding
Injection logic updates the PD field of the status word. The status word can be read at any time during
injection without affecting current data block transfers. However, a CPU is able to calculate how much
data that is required to inject a complete block of data (at least BLOCKO + BLOCKL bytes), so reading
the status word is for software development and debug only. Writing status word before finishing a
previous data block will cause that frame to be aborted. Frames are also aborted if they do not start with
SOF or end with EOF indications.
As long as the status word is not written, multiple writes to the injection region are treated as data
belonging to the same block. This means multiple bursts of data words can be written between each
injection status word update.
Software can abort frames by writing to injection status with ABORT field set. All other status word fields
are ignored. When a frame is aborted, the already injected data is removed from the queuing system.
4.8
VCore-III System Peripherals
This section describes the subblocks of the VCore-III system. Although the subblocks are primarily
intended to be used by the VCore-III CPU, an external CPU can also access and control them through
the shared bus.
4.8.1
SI Boot Controller
The SPI boot master allows booting from a Flash that is connected to the serial interface. For information
about how to write to the serial interface, see SI Master Controller, page 335. For information about using
an external CPU to access device registers using the serial interface, see Serial Interface in Slave Mode,
page 312.
The following table lists the registers associated with the SI boot controller.
Table 245 •
SI Boot Controller Configuration Registers
Register
Description
ICPU_CFG::SPI_MST_CFG
Serial interface speed and address width
ICPU_CFG::SW_MODE
Legacy manual control of the serial interface pins
ICPU_CFG::GENERAL_CTRL
SI interface ownership
[31:20]
[15:0]
16
17
18
19
BLOCKL: The amount of frame data (bytes) that
will be written for this block. The CPU is allowed to
write more data than this, additional data will be
ignored.
SOF: Start of frame, set to indicate that this block
contains start of a frame.
EOF: End of frame, set to indicate that this block
contains end of a frame.
ABORT: Set to abort active frame transfer. The
current frame will be aborted and removed from
Queuing System.
PD: Injection done, is set by the injection logic
when enough data has been received for this block
of data (BLOCKO+BLOCKL). If set when writing
status word, then this is treated as if ABORT had
been set.
BLOCKO: The amount of dummy bytes (non-frame
data) to expect before the frame data. The dummy
data will be ignored.
BLOCKL
BLOCKO



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