VSC7440 datasheet(356/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

339

4.8.2.3

SIMC SSP 2x Transfers

4.8.2.4

SIMC Interrupts

The SI master controller has five interrupt sources:

•

RXF interrupt is asserted when the fill level of the receive FIFO (available in RXFLR) exceeds the

programmable level set in RXFTLR. This interrupt is non-sticky; it is deasserted when fill level is

decreased below the programmable level.

•

RXO interrupt is asserted on receive FIFO overflow. This interrupt is cleared by reading the RXOICR

•

RXU interrupt is asserted when reading from an empty receive FIFO. This interrupt is cleared by

reading the RXUICR register.

•

TXO interrupt is asserted when writing to a full transmit FIFO. This interrupt is cleared by reading the

TXOICR register.

•

TXE interrupt is asserted when the fill level of the transmit FIFO (available in TXFLR) is below the

programmable level set in TXFTLR. This interrupt is non-sticky; it is deasserted when fill level is

increased above the programmable level.

The raw (unmasked) status of these interrupts is available in the RISR register. Each of the interrupts can

be individually masked by the IMR register. All interrupts are enabled by default. The currently active

interrupts are shown in the ISR register.

If the RXO, RXU, and TXO interrupts occur during normal use of the SI master controller, it is an

indication of software problems.

Interrupt is asserted towards the VCore-III interrupt controller when any enabled interrupt is asserted and

the SI master controller is enabled.

4.8.2.5

SIMC Programming Example

This example shows how to use the SI master controller to interface with the SI slave of another device.

The slave device will be initialized for big endian/most significant bit first mode and then the

DEVCPU_GCB::GPR register is written with the value 0x01234567. It is assumed that the other device’s

SI slave is connected on SI_nCS1 (and that appropriate GPIO alternate function has been enabled).

The SI slave is using a 24-bit address field and a 32-bit data field. This example uses 4 x 16-bit data

frames to transfer the write-access. This means that 8 bits too much will be transferred, this is not a

problem for the Microsemi SI slave interface; it ignores data above and beyond the 56 bit required for a

write-access.

For information about initialization and how to calculate the 24-bit SI address field, see Serial Interface in

Slave Mode, page 312. The address-field when writing DEVCPU_GCB::GPR is 0x804001 (including

write-indication).

The following steps are required to bring up the SI master controller and write twice to the SI slave

device.

Important The following procedure disconnects the SI boot master from the SI interface. Booting must

be done before attempting to overtake the boot-interface.

SI_nCS0

SI_CLK

SI_DO

SI_DI

First frame

105

Second frame

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