VSC7440 datasheet(357/444 Pages) MICROSEMI

357 / 444 page

VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

340

Write GENERAL_CTRL.IF_SI_OWNER = 2 to make SI master controller the owner of the SI

interface.

Write BAUDR = 250 to get 1 MHz baud rate.

Write SER = 2 to use SI_nCS1.

Write CTRLR0 = 0x10F for 16-bit data frame and transmit only.

Write SIMCEN = 1 to enable the SI master controller.

Write DR[0] = 0x8000, 0x0081, 0x8181, 0x8100 to configure SI slave for big endian / most significant

bit first mode.

Wait for SR.TFE = 1 and SR.BUSY = 0 for chip select to deassert between accesses to the SI slave.

Write DR[0] = 0x8040, 0x0101, 0x2345, 0x6700 to write DEVCPU_GCB::GPR in slave device.

Wait for SR.TFE = 1 and SR.BUSY = 0, then disable the SI master controller by writing SIMCEN = 0.

When reading from the SI slave, CTRLR0.TMOD must be configured for transmit and receive. One-byte

padding is appropriate for a 1 MHz baud rate.

4.8.3

DDR3/DDR3L Memory Controller

This section provides information about how to configure and initialize the DDR3/DDR3L memory

controller.

The following table lists the registers associated with the memory controller.

The memory controller works with JEDEC-compliant DDR3/DDR3L memory modules. The controller

runs 312.50 MHz and supports one or two byte lanes in either single or dual row configurations (one or

two chip selects). The controller supports up to 16 address bits. The maximum amount of physical

memory that can be attached to the controller is 1 gigabyte.

The memory controller supports ECC encoding/decoding by using one of the two lanes for ECC

information. Enabling ECC requires that both byte lanes are populated. When ECC is enabled, half the

total physical memory is available for software use; the other half is used for ECC information.

Table 249 •

DDR3/DDR3L Controller Registers

Description

ICPU_CFG::RESET

Reset Control

ICPU_CFG::MEMCTRL_CTRL

Control

ICPU_CFG::MEMCTRL_CFG

Configuration

ICPU_CFG::MEMCTRL_STAT

Status

ICPU_CFG::MEMCTRL_REF_PERIOD

Refresh period configuration

ICPU_CFG::MEMCTRL_ZQCAL

DDR3/DDR3L ZQ-calibration

ICPU_CFG::MEMCTRL_TIMING0

Timing configuration

ICPU_CFG::MEMCTRL_TIMING1

Timing configuration

ICPU_CFG::MEMCTRL_TIMING2

Timing configuration

ICPU_CFG::MEMCTRL_TIMING3

Timing configuration

ICPU_CFG::MEMCTRL_MR0_VAL

Mode register 0 value

ICPU_CFG::MEMCTRL_MR1_VAL

Mode register 1 value

ICPU_CFG::MEMCTRL_MR2_VAL

Mode register 2 value

ICPU_CFG::MEMCTRL_MR3_VAL

Mode register 3 value

ICPU_CFG::MEMCTRL_TERMRES_CTRL

Termination resistor control

ICPU_CFG::MEMCTRL_DQS_DLY

DQS window configuration

ICPU_CFG::MEMPHY_CFG

SSTL configuration

ICPU_CFG::MEMPHY_ZCAL

SSTL calibration

VSC7440 Datasheet(PDF) 357 Page - Microsemi Corporation

VSC7440 Datasheet(HTML) 357 Page - Microsemi Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL