VSC7440 datasheet(382/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

365

The following table lists the registers associated with the interrupt controller.

The interrupt controller maps interrupt sources from VCore-III and switch core blocks, port modules, and

external interrupt inputs to four interrupt destinations. Two interrupt destinations are mapped to the

VCore-III CPU, and two can be transmitted from the device using the overlaid functions on GPIOs or

using PCIe inband interrupt signaling.

The following table lists the available interrupt sources in the device.

Table 271 •

Interrupt Controller Registers

Description

ICPU_CFG::INTR_RAW

Current value of interrupt inputs

ICPU_CFG::INTR_BYPASS

Forces non-sticky function

ICPU_CFG::INTR_TRIGGER

Configures edge or level sensitive events

ICPU_CFG::INTR_FORCE

Forces events (for software debug)

ICPU_CFG::INTR_STICKY

Currently logged events

ICPU_CFG::INTR_ENA

Enables interrupt sources

ICPU_CFG::INTR_ENA_CLR

Atomic clear of bits in INTR_ENA

ICPU_CFG::INTR_ENA_SET

Atomic set of bits in INTR_ENA

ICPU_CFG::INTR_IDENT

Currently enabled and interrupting sources

ICPU_CFG::DST_INTR_MAP

Mapping of interrupt sources to destinations

ICPU_CFG::DST_INTR_IDENT

Currently enabled, mapped, and interrupting sources per destination

ICPU_CFG::DEV_INTR_POL

Polarity of module interrupt inputs

ICPU_CFG::DEV_INTR_RAW

Current value of module interrupts

ICPU_CFG::DEV_INTR_BYPASS

Forces non-sticky function for module interrupts

ICPU_CFG::DEV_INTR_TRIGGER

Configures edge or level sensitive events for module interrupts

ICPU_CFG::DEV_INTR_STICKY

Currently logged module interrupt events

ICPU_CFG::DEV_INTR_ENA

Enables module interrupts

ICPU_CFG::DEV_INTR_IDENT

Currently interrupting and enabled module interrupts

ICPU_CFG::EXT_SRC_INTR_POL

Polarity of external interrupt inputs.

ICPU_CFG::EXT_DST_INTR_POL

Polarity of external interrupt outputs.

ICPU_CFG::EXT_DST_INTR_DRV

Drive mode for external interrupt outputs

Table 272 •

Interrupt Sources

Source Name

Description

DEV

Aggregated port module interrupt. This interrupt is asserted if there is an active and enabled interrupt

from any of the device’s port modules. See Port Module Interrupts.

This interrupt has bit index 0 in INTR_* and DST_INTR_* registers.

EXT_SRC0

External interrupt source 0. See External Interrupts.

This interrupt has bit index 1 in INTR_* and DST_INTR_* registers.

EXT_SRC1

External interrupt source 1. See External Interrupts.

This interrupt has bit index 2 in INTR_* and DST_INTR_* registers.

TIMER0

Timer 0 interrupt. See Timers.

This interrupt has bit index 3 in INTR_* and DST_INTR_* registers.

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