VSC7440 datasheet(426/444 Pages) MICROSEMI

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Pin Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

409

7.2.13

Twisted Pair Interface

The following table lists the pins associated with the twisted pair interface.

CLKOUTPLL2_N

CLKOUTPLL2_P

LVDS

PLL2 clock output. Leave floating if not used.

REFCLK_N

REFCLK_P

REFCLK2_N

REFCLK2_P

ITD

LVDS

LVCMOS

Reference clock inputs.

The inputs can be either differential or single-ended.

In differential mode (LVDS), REFCLK_P/REFCLK2_P is the true

part of the differential signal, and REFCLK_N/REFCLK_N is the

complement part of the differential signal.

In single-ended mode (LVCMOS), REFCLK_P/REFCLK2_P is used

as single-ended LVTTL input. REFCLK_N/REFCLK2_N should be

left floating, and the PLL registers must be configured for single-

ended operation.

Required applied frequency depends on REFCLK_CONF[2:0] and

REFCLK2_CONF[2:0] input state.

Table 337 •

Twisted Pair Interface Pins

Name

I/O

Type

Description

P0_D0P

P1_D0P

I/O

ADIFF Tx/Rx channel A positive signal.

Positive differential signal connected to the positive primary side of the transformer.

This pin signal forms the positive signal of the A data channel. In all three speeds,

these pins generate the secondary side signal, normally connected to RJ-45 pin 1.

P0_D0N

P1_D0N

I/O

ADIFF Tx/Rx channel A negative signal.

Negative differential signal connected to the negative primary side of the transformer.

This pin signal forms the negative signal of the A data channel. In all three speeds,

these pins generate the secondary side signal, normally connected to RJ-45 pin 2.

P0_D1P

P1_D1P

I/O

ADIFF Tx/Rx channel B positive signal.

Positive differential signal connected to the positive primary side of the transformer.

This pin signal forms the positive signal of the B data channel. In all three speeds,

these pins generate the secondary side signal, normally connected to RJ-45 pin 3.

P0_D1N

P1_D1N

I/O

ADIFF Tx/Rx channel B negative signal.

Negative differential signal connected to the negative primary side of the transformer.

This pin signal forms the negative signal of the B data channel. In all three speeds,

these pins generate the secondary side signal, normally connected to RJ-45 pin 6.

P0_D2P

P1_D2P

I/O

ADIFF Tx/Rx channel C positive signal.

Positive differential signal connected to the positive primary side of the transformer.

This pin signal forms the positive signal of the C data channel. In 1000-Mbps mode,

these pins generate the secondary side signal, normally connected to RJ-45 pin 4

(pins not used in 10/100 Mbps modes).

P0_D2N

P1_D2N

I/O

ADIFF Tx/Rx channel C negative signal.

Negative differential signal connected to the negative primary side of the transformer.

This pin signal forms the negative signal of the C data channel. In 1000-Mbps mode,

these pins generate the secondary side signal, normally connected to RJ-45 pin 5

(pins not used in 10/100 Mbps modes).

Table 336 •

System Clock Interface Pins (continued)

Name

I/O

Type

Level

Description

VSC7440 Datasheet(PDF) 426 Page - Microsemi Corporation

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