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VSC7440 Datasheet(PDF) 422 Page - Microsemi Corporation

Part # VSC7440
Description  L2/L3 Enterprise Gigabit Ethernet Switch with 10 Gbps Links
PDF  444 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC7440 Datasheet(HTML) 422 Page - Microsemi Corporation

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Pin Descriptions
VMDS-10492 VSC7440 Datasheet Revision 4.2
405
7.2.2
General-Purpose Inputs and Outputs
The following table lists the general-purpose I/O (GPIO) pins. Leave GPIO pins unconnected when not in
use.
Many of the GPIO pins serve multiple functions. For more information about the overlaid functions and
how to configure them, GPIO Overlaid Functions, page 352.
7.2.3
JTAG Interface
The following table lists the pins associated with the JTAG interface. The JTAG interface can be
connected to the boundary scan TAP controller or the internal VCore-III TAP controller for software
debug as described under the JTAG_ICE_nEN signal.
The JTAG signals are not 5 V tolerant.
7.2.4
MII Management Interface
The following table lists the pins associated with the MII Management interface. The MIIM signals are
GPIO alternate functions. For more information about the GPIO pin mapping, see GPIO Overlaid
Functions, page 352.
Table 326 •
GPIO Pins
Name
I/O
Level
Description
GPIO_[36:0]
I/O
CMOS
General-purpose inputs and outputs.
Table 327 •
JTAG Interface Pins
Name
I/O
Type
Level
Description
JTAG_ICE_nEN
I
ST, 3V
CMOS 0: Enables VCore-III debug interface over the JTAG interface.
1: Enables normal JTAG I/O over the JTAG interface.
JTAG_ICE_nEN should be pulled either high or low using a
resistor of 10 k
Ω or less to enable the desired operating mode.
JTAG_nTRST
I
ST, 3V
CMOS JTAG test reset, active low. For normal device operation,
JTAG_nTRST should be pulled low.
JTAG_TCK
I
ST, 3V
CMOS JTAG clock.
JTAG_TDI
I
ST, 3V
CMOS JTAG test data in.
JTAG_TDO
O
OZ, 3V
CMOS JTAG test data out.
JTAG_TMS
I
ST, 3V
CMOS JTAG test mode select.
Table 328 •
MII Management Interface Pins
Name
I/O
Type
Level
Description
MDC1
I/O
3V
CMOS
Management data clock.
MDC1 is sourced by the station management entity (the device) to
the PHY as the timing reference for transfer of information on the
MDIO1 signal. MDC1 is an aperiodic signal.
MDIO1
I/O
3V
CMOS
Management data input/output.
MDIO1 is a bidirectional signal between a PHY and the device, used
to transfer control and status information. Control information is
driven by the device synchronously with respect to MDC1 and is
sampled synchronously by the PHY. Status information is driven by
the PHY synchronously with respect to MDC1 and is sampled
synchronously by the device.



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