VSC7440 datasheet(421/444 Pages) MICROSEMI

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Pin Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

404

7.2.1

DDR SDRAM Interface

The following table lists the pins associated with the DDR3/DDR3L SDRAM interface.

Termination differential

Internal differential termination

Table 325 •

DDR3/DDR3L SDRAM Pins

Name

I/O

Type

Level

Description

DDR_A[15:0]

SSTL

SDRAM address outputs.

Provide row and column addresses to the SDRAM.

DDR_BA[2:0]

SSTL

SDRAM bank address outputs.

DDR_BA[2:0] define to which bank an ACTIVE, READ, WRITE, or

PRECHARGE command is applied.

DDR_CK

DDR_CKn

DIFF

SSTL

SDRAM differential clock. Differential clock to external SDRAM.

DDR_CK is the true part of the differential signal.

DDR_CKn is the complement part.

DDR_CKE

SSTL

SDRAM clock enable.

0: Disables clock in external SDRAM.

1: Enables clock in external SDRAM.

DDR_nCS[1:0]

SSTL

SDRAM chip selects. Active low.

DDR_DQ[15:0]

I/O

SSTL

SDRAM data bus.

DDR_LDM

DDR_UDM

SSTL

SDRAM data mask outputs.

DDR_LDM and DDR_UDM are mask signals for data written to the

SDRAM. DDR_LDM corresponds to data on DDR_DQ[7:0], and

DDR_UDM corresponds to data on DDR_DQ[15:8].

DDR_LDQS

DDR_LDQSn

DDR_UDQS

DDR_UDQSn

I/O

DIFF,

SSTL

SDRAM differential data strobes.

Bidirectional differential signal that follows data direction. Used by

SDRAM to capture data on write operations. Edge-aligned with data

from SDRAM during read operations and used by the device to

capture data.

DDR_LDQS corresponds to data on DDR_DQ[7:0], and DDR_UDQS

corresponds to data on DDR_DQ[15:8].

DDR_nRAS

DDR_nCAS

DDR_nWE

SSTL

SDRAM command outputs.

DDR_nRAS, DDR_nCAS, and DDR_nWE (along with DDR_nCS)

define the command being entered.

DDR_ODT

SSTL

Control signal for the attached DDR3/DDR3L SDRAM devices on-die

termination.

DDR_Rext

ABIAS

Analog External DDR impedance calibration.

Connect the pin through an external 240

Ω ±1% resistor to ground.

DDR_Vref

ABIAS

Analog Input reference voltage.

Provides the input switching reference voltage to the SSTL DDR

signals.

Table 324 •

Pin Type Symbol Definitions (continued)

Symbol

Pin Type

Description

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