USB7002 datasheet(46/56 Pages) MICROCHIP

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USB7002

DS00002670D-page 46

 2018-2019 Microchip Technology Inc.

9.6.8

SPI/SQI MASTER TIMING

This section specifies the SPI/SQI master timing requirements for the device.

FIGURE 9-5:

SPI/SQI MASTER TIMING

TABLE 9-7:

SPI/SQI MASTER TIMING (30 MHZ OPERATION)

Symbol

Description

Min

Typ

Max

Units

tfc

Clock frequency

MHz

tceh

Chip enable (SPI_CE_N) high time

100

tclq

Clock to input data

tdh

Input data hold time

tos

Output setup time

toh

Output hold time

tov

Clock to output valid

tcel

Chip enable (SPI_CE_N) low to first clock

tceh

Last clock to chip enable (SPI_CE_N) high

TABLE 9-8:

SPI/SQI MASTER TIMING (60 MHZ OPERATION)

Symbol

Description

Min

Typ

Max

Units

tfc

Clock frequency

MHz

tceh

Chip enable (SPI_CE_N) high time

tclq

Clock to input data

tdh

Input data hold time

tos

Output setup time

toh

Output hold time

tov

Clock to output valid

tcel

Chip enable (SPI_CE_N) low to first clock

tceh

Last clock to chip enable (SPI_CE_N) high

SPI_CLK

SPI_D[3:0] (in)

SPI_D[3:0] (out)

SPI_CE_N

tcel

tfc

Output

data valid

tclq

tceh

tdh

toh

tos

tov

toh

Output

data valid

Input

data valid

tceh

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