SAMV71Q21 datasheet(6/41 Pages) MICROCHIP

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Silicon Issue Summary

Table 1-1. Silicon Issue Summary

Module

Item and Feature

Summary

Affected Silicon

Revisions

AFEC

2.1 Write Protection

The AFEC_CSELR register is not write-

protected.

AFEC

2.2 Performance

The AFEC is sensitive to noise. Too

much noise may lead to reduced AFEC

performance, especially INL, DNL and

SNR.

AFEC

2.3 AOFF bit

Changing the AOFF bit in the

AFEC_COCR register during

conversions is not safe.

ARM Cortex-

3.1 ARM® Cortex®-M7

All issues related to the ARM r0p1 (for

MRLA) and r1p1 (and MRLB) cores are

described on the ARM site.

Boundary

Scan Mode

4.1 Internal Regulator

The internal regulator is OFF in

Boundary Scan mode.

Device

5.1 AHB Peripheral

(AHBP) Port Frequency

Ratio

Peripheral accesses done through the

AHBP with a Core/Bus ratio of 1/3 and

1/4 may lead to unpredictable results.

Device

5.2 AHB Slave (AHBS)

Port Latency Access

DMA accesses done through the AHBS

to the TCM with a Core/Bus ratio of 1/2,

1/3, and 1/4 may lead to latency due to

one Wait state added to the access from

the bus to AHBS.

XDMAC

6.1 TCM Accesses

If TCM accesses are generated through

the AHBS port of the core, only 32-bit

accesses are supported.

XDMAC

6.2 Byte and Half-Word

Accesses

If XDMAC is used to transfer 8-bit or 16-

bit data in Fixed Source Address mode

or Fixed Destination Address mode,

source and destination addresses are

incremented by 8-bit or 16-bit.

XDMAC

6.3 Request Overflow

Error

When a DMA memory-to-memory

transfer is performed, if the hardware

request line selected by the field PERID

bit in the XDMAC_CCx register toggles

when the copy is enabled, the ROIS bit

in the XDMAC_CISx register is set

incorrectly.

SAM E70/S70/V70/V71 Family

Silicon Issue Summary

Datasheet Errata

DS80000767C-page 6

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