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LP4063 Datasheet(PDF) 2 Page - Lowpower Semiconductor inc |
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LP4063 Datasheet(HTML) 2 Page - Lowpower Semiconductor inc |
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2 / 6 page ![]() LP4063-01 Oct.-2018 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 2 of 6 Preliminary Datasheet LP4063 Functional Pin Description Package Type Pin Configurations SOT23-5 1 3 5 4 CHRG ISET SOT23-5 TOP VIEW 2 GND BAT VIN Pin Description No. NAME DESCRIPTION 1 CHRG Open-Drain Charge Status Output. When the battery is charging, the CHRG pin is pulled low by an internal NMOS. When the charge cycle is completed, the pin could be pulled High by an external pull high resistor. 2 GND GND is the connection to system ground. 3 BAT BAT is the connection to the battery. Typically a 10µF Tantalum capacitor is needed for stability when there is no battery attached. When a battery is attached, only a 1uF ceramic capacitor is required. 4 VIN VIN is the input power source. Connect to a wall adapter. 5 ISET Charge Current Program. The charge current is programmed by connecting a 1% resistor(RISET) to ground. |
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