PIC16F913 datasheet(109/272 Pages) MICROCHIP

109 / 272 page

Preliminary

DS41250E-page 107

PIC16F917/916/914/913

9.3

LCD Multiplex Types

The LCD driver module can be configured into four

multiplex types:

• Static (only COM0 used)

• 1/2 multiplex (COM0 and COM1 are used)

• 1/3 multiplex (COM0, COM1 and COM2 are used)

• 1/4 multiplex (all COM0, COM1, COM2 and COM3

are used)

The LMUX<1:0> setting decides the function of RB5,

RA2 or either RA3 or RD0 pins (see Table 9-1 for

details).

If the pin is a digital I/O, the corresponding TRIS bit

controls the data direction. If the pin is a COM drive,

then the TRIS setting of that pin is overridden.

TABLE 9-1:

RA3, RA2, RB5 FUNCTION

9.4

Segment Enables

The LCDSEn registers are used to select the pin

function for each segment pin. The selection allows

each pin to operate as either an LCD segment driver or

as one of the pin’s alternate functions. To configure the

pin as a segment pin, the corresponding bits in the

LCDSEn registers must be set to ‘1’.

If the pin is a digital I/O, the corresponding TRIS bit

controls the data direction. Any bit set in the LCDSEn

registers overrides any bit settings in the corresponding

TRIS register.

9.5

Pixel Control

The LCDDATAx registers contain bits which define the

state of each pixel. Each bit defines one unique pixel.

LCDDATAx registers to the respective common and

segment signals.

Any LCD pixel location not being used for display can

be used as general purpose RAM.

9.6

LCD Frame Frequency

The rate at which the COM and SEG outputs change is

called the LCD frame frequency.

TABLE 9-2:

FRAME FREQUENCY

FORMULAS

TABLE 9-3:

APPROXIMATE FRAME

FREQUENCY (IN Hz) USING

FOSC @ 8 MHz, TIMER1 @

32.768 kHz OR INTOSC

Note:

On a Power-on Reset, the LMUX<1:0>

bits are ‘11’.

LMUX

<1:0>

RA3/RD0(1)

RA2

RB5

Digital I/O

COM1 Driver

Digital I/O

COM2 Driver COM1 Driver

COM3 Driver COM2 Driver COM1 Driver

Note 1:

RA3 for PIC16F913/916, RD0 for

PIC16F914/917

Note:

On a Power-on Reset, these pins are

configured as digital I/O.

Multiplex

Frame Frequency =

Static

Clock source/(4 x 1 x (LP<3:0> + 1))

1/2

Clock source/(2 x 2 x (LP<3:0> + 1))

1/3

Clock source/(1 x 3 x (LP<3:0> + 1))

1/4

Clock source/(1 x 4 x (LP<3:0> + 1))

Note:

Clock source is FOSC/8192, T1OSC/32 or

LFINTOSC/32.

LP<3:0>

Static

1/2

1/3

1/4

114

364

451

543

637

732

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