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PIC16F913 Datasheet(PDF) 123 Page - Microchip Technology

Part # PIC16F913
Description  28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology
PDF  272 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16F913 Datasheet(HTML) 123 Page - Microchip Technology

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© 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 121
PIC16F917/916/914/913
9.8
LCD Interrupts
The LCD timing generation provides an interrupt that
defines the LCD frame timing. This interrupt can be
used to coordinate the writing of the pixel data with the
start of a new frame. Writing pixel data at the frame
boundary allows a visually crisp transition of the image.
This interrupt can also be used to synchronize external
events to the LCD.
A new frame is defined to begin at the leading edge of
the COM0 common signal. The interrupt will be set
immediately
after the
LCD
controller
completes
accessing all pixel data required for a frame. This will
occur at a fixed interval before the frame boundary
(TFINT), as shown in Figure 9-16. The LCD controller
will begin to access data for the next frame within the
interval from the interrupt to when the controller begins
to access data after the interrupt (TFWR). New data
must be written within TFWR, as this is when the LCD
controller will begin to access the data for the next
frame.
When the LCD driver is running with Type-B waveforms
and the LMUX<1:0> bits are not equal to ‘00’, there are
some additional issues that must be addressed. Since
the DC voltage on the pixel takes two frames to maintain
zero volts, the pixel data must not change between
subsequent frames. If the pixel data were allowed to
change, the waveform for the odd frames would not
necessarily be the complement of the waveform
generated in the even frames and a DC component
would be introduced into the panel. Therefore, when
using Type-B waveforms, the user must synchronize the
LCD pixel updates to occur within a subframe after the
frame interrupt.
To correctly sequence writing while in Type-B, the
interrupt will only occur on complete phase intervals. If the
user attempts to write when the write is disabled, the
WERR (LCDCON<5>) bit is set.
FIGURE 9-16:
WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY CYCLE DRIVE
(EXAMPLE – TYPE-B, NON-STATIC)
Note:
The interrupt is not generated when the
Type-A waveform is selected and when the
Type-B
with
no
multiplex
(static)
is
selected.
Frame
Boundary
Frame
Boundary
LCD
Interrupt
Occurs
Controller Accesses
Next Frame Data
TFINT
TFWR
TFWR =TFRAME/2*(LMUX<1:0> + 1) + TCY/2
TFINT =(TFWR/2 – (2 TCY + 40 ns))
→ minimum = 1.5(TFRAME/4) – (2 TCY + 40 ns)
(TFWR/2 – (1 TCY + 40 ns))
→ maximum = 1.5(TFRAME/4) – (1 TCY + 40 ns)
Frame
Boundary
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
COM0
COM1
COM2
COM3
2 Frames



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