PIC16F913 datasheet(136/272 Pages) MICROCHIP

136 / 272 page

PIC16F917/916/914/913

DS41250E-page 134

Preliminary

11.2.2

USART ASYNCHRONOUS

RECEIVER

The receiver block diagram is shown in Figure 11-4.

The

data

received

the

RC7/RX/DT/SDI/SDA/SEG8 pin and drives the data

recovery block. The data recovery block is actually a

high-speed shifter, operating at x16 times the baud

rate; whereas the main receive serial shifter operates

at the bit rate or at FOSC.

Once Asynchronous mode is selected, reception is

enabled by setting bit CREN (RCSTA<4>).

The heart of the receiver is the Receive (Serial) Shift

received data in the RSR is transferred to the RCREG

bit, RCIF (PIR1<5>), is set. The actual interrupt can be

enabled/disabled by setting/clearing enable bit, RCIE

(PIE1<5>). Flag bit RCIF is a read-only bit which is

cleared by the hardware. It is cleared when the RCREG

double-buffered register (i.e., it is a two-deep FIFO). It

is possible for two bytes of data to be received and

transferred to the RCREG FIFO and a third byte to

begin shifting to the RSR register. On the detection of

the Stop bit of the third byte, if the RCREG register is

still full, the Overrun Error bit, OERR (RCSTA<1>), will

be set. The word in the RSR will be lost. The RCREG

the FIFO. Overrun bit OERR has to be cleared in soft-

ware. This is done by resetting the receive logic (CREN

is cleared and then set). If bit OERR is set, transfers

from the RSR register to the RCREG register are inhib-

ited and no further data will be received. It is, therefore,

essential to clear error bit OERR if it is set. Framing

error bit, FERR (RCSTA<2>), is set if a Stop bit is

detected as clear. Bit FERR and the 9th receive bit are

buffered the same way as the receive data. Reading

the RCREG will load bits RX9D and FERR with new

values, therefore, it is essential for the user to read the

RCSTA register before reading the RCREG register in

order not to lose the old FERR and RX9D information.

When setting up an Asynchronous Reception, follow

these steps:

Initialize the SPBRG register for the appropriate

baud rate. If a high-speed baud rate is desired,

set bit BRGH (Section 11.1 “USART Baud

Rate Generator (BRG)”).

Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

If interrupts are desired, then set enable bit

RCIE.

If 9-bit reception is desired, then set bit RX9.

Enable the reception by setting bit CREN.

Flag bit RCIF will be set when reception is com-

plete and an interrupt will be generated if enable

bit RCIE is set.

Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

Read the 8-bit received data by reading the

RCREG register.

If any error occurred, clear the error by clearing

enable bit CREN.

10. If using interrupts, ensure that GIE and PEIE

(bits 7 and 6) of the INTCON register are set.

PIC16F913 Datasheet(PDF) 136 Page - Microchip Technology

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