PIC16F913 datasheet(146/272 Pages) MICROCHIP

146 / 272 page

PIC16F917/916/914/913

DS41250E-page 144

Preliminary

12.1

A/D Configuration and Operation

There are three registers available to control the

functionality of the A/D module:

ANSEL (Register 12-1)

ADCON0 (Register 12-2)

ADCON1 (Register 12-3)

12.1.1

ANALOG PORT PINS

The ANS<7:0> bits (ANSEL<7:0>) and the TRIS bits

control the operation of the A/D port pins. Set the

corresponding TRIS bits to set the pin output driver to

its high-impedance state. Likewise, set the correspond-

ing ANSEL bit to disable the digital input buffer.

12.1.2

CHANNEL SELECTION

There are up to eight analog channels on the

PIC16F917/916/914/913, AN<7:0>. The CHS<2:0> bits

(ADCON0<4:2>) control which channel is connected to

the sample and hold circuit.

12.1.3

VOLTAGE REFERENCE

There are two options for each reference to the A/D

converter, VREF+ and VREF-. VREF+ can be connected to

either VDD or an externally applied voltage. Alternatively,

VREF- can be connected to either VSS or an externally

applied voltage. VCFG<1:0> bits are used to select the

reference source.

12.1.4

CONVERSION CLOCK

The A/D conversion cycle requires 11 TAD. The source

of the conversion clock is software selectable via the

ADCS bits (ADCON1<6:4>). There are seven possible

clock options:

•FOSC/2

•FOSC/4

•FOSC/8

•FOSC/16

•FOSC/32

•FOSC/64

•FRC (dedicated internal oscillator)

For correct conversion, the A/D conversion clock

(1/TAD) must be selected to ensure a minimum TAD of

1.6

μs. Table 12-1 shows a few TAD calculations for

selected frequencies.

TABLE 12-1:

TAD vs. DEVICE OPERATING FREQUENCIES

Note:

Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

A/D Clock Source (TAD)

Device Frequency

Operation

ADCS<2:0>

20 MHz

5 MHz

4 MHz

1.25 MHz

2 TOSC

000

100 ns(2)

400 ns(2)

500 ns(2)

1.6

μs

4 TOSC

100

200 ns(2)

800 ns(2)

1.0

μs(2)

3.2

μs

8 TOSC

001

400 ns(2)

1.6

μs2.0 μs6.4 μs

16 TOSC

101

800 ns(2)

3.2

μs4.0 μs

12.8

μs(3)

32 TOSC

010

1.6

μs6.4 μs

8.0

μs(3)

25.6

μs(3)

64 TOSC

110

3.2

μs

12.8

μs(3)

16.0

μs(3)

51.2

μs(3)

A/D RC

x11

2-6

μs(1,4)

2-6

μs(1,4)

2-6

μs(1,4)

2-6

μs(1,4)

Legend: Shaded cells are outside of recommended range.

Note 1:

The A/D RC source has a typical TAD time of 4

μs for VDD > 3.0V.

These values violate the minimum required TAD time.

For faster conversion times, the selection of another clock source is recommended.

When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the

conversion will be performed during Sleep.

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