PIC16F913 datasheet(158/272 Pages) MICROCHIP

158 / 272 page

PIC16F917/916/914/913

DS41250E-page 156

Preliminary

13.1.2

READING THE DATA EEPROM

MEMORY

To read a data memory location, the user must write the

address to the EEADRL register, clear the EEPGD

control bit (EECON1<7>), and then set control bit RD

(EECON1<0>). The data is available in the very next

cycle, in the EEDATL register; therefore, it can be read

in the next instruction. EEDATL will hold this value until

another read or until it is written to by the user (during

a write operation).

EXAMPLE 13-1:

DATA EEPROM READ

13.1.3

WRITING TO THE DATA EEPROM

MEMORY

To write an EEPROM data location, the user must first

write the address to the EEADRL register and the data

to the EEDATL register. Then the user must follow a

specific sequence to initiate the write for each byte.

The write will not initiate if the sequence described below

is not followed exactly (write 55h to EECON2, write AAh

to EECON2, then set WR bit) for each byte. Interrupts

should be disabled during this code segment.

Additionally, the WREN bit in EECON1 must be set to

enable write. This mechanism prevents accidental

writes to data EEPROM due to errant (unexpected)

code execution (i.e., lost programs). The user should

keep the WREN bit clear at all times, except when

updating EEPROM. The WREN bit is not cleared

by hardware.

After a write sequence has been initiated, clearing the

WREN bit will not affect this write cycle. The WR bit will

be inhibited from being set unless the WREN bit is set.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. EEIF must be

cleared by software.

The steps to write to EEPROM data memory are:

If step 10 is not implemented, check the WR bit

to see if a write is in progress.

Write the address to EEADR. Make sure that the

address is not larger than the memory size of

the device.

Write the 8-bit data value to be programmed in

the EEDATA register.

Clear the EEPGD bit to point to EEPROM data

memory.

Set the WREN bit to enable program operations.

Disable interrupts (if enabled).

Execute the special five instruction sequence:

• Write 55h to EECON2 in two steps (first to W,

then to EECON2)

• Write AAh to EECON2 in two steps (first to

W, then to EECON2)

• Set the WR bit

Enable interrupts (if using interrupts).

Clear the WREN bit to disable program

operations.

10. At the completion of the write cycle, the WR bit

is cleared and the EEIF interrupt flag bit is set.

(EEIF must be cleared by firmware.) If step 1 is

not implemented, then firmware should check

for EEIF to be set, or WR to clear, to indicate the

end of the program cycle.

EXAMPLE 13-2:

DATA EEPROM WRITE

BSF

STATUS,RP1

;

BCF

STATUS,RP0

; Bank 2

MOVF

DATA_EE_ADDR,W ; Data Memory

MOVWF

EEADR

; Address to read

BSF

STATUS,RP0

; Bank 3

BCF

EECON1,EEPGD

; Point to Data

; memory

BSF

EECON1,RD

; EE Read

BCF

STATUS,RP0

; Bank 2

MOVF

EEDATA,W

; W = EEDATA

BSF

STATUS,RP1

;

BSF

STATUS,RP0

BTFSC

EECON1,WR

;Wait for write

GOTO

$-1

;to complete

BCF

STATUS,RP0

;Bank 2

MOVF

DATA_EE_ADDR,W;Data Memory

MOVWF

EEADR

;Address to write

MOVF

DATA_EE_DATA,W;Data Memory Value

MOVWF

EEDATA

;to write

BSF

STATUS,RP0

;Bank 3

BCF

EECON1,EEPGD ;Point to DATA

;memory

BSF

EECON1,WREN

;Enable writes

BCF

INTCON,GIE

;Disable INTs.

MOVLW

55h

;

MOVWF

EECON2

;Write 55h

MOVLW

AAh

;

MOVWF

EECON2

;Write AAh

BSF

EECON1,WR

;Set WR bit to

;begin write

BSF

INTCON,GIE

;Enable INTs.

BCF

EECON1,WREN

;Disable writes

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