June 2005

ASM2P3805AH

rev 0.2

Alliance Semiconductor

2575, Augustine Drive

• Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com

Notice: The information in this document is subject to change without notice.

3.3V CMOS Buffer Clock Driver

Features

Advanced CMOS Technology

Guaranteed low skew < 500pS (max.)

Very low duty cycle distortion < 1.0nS (max)

Very low CMOS power levels

TTL compatible inputs and outputs

Inputs can be driven from 3.3V or 5V components

Two independent output banks with 3-state control

1:5 fanout per bank

"Heartbeat" monitor output

Available in SSOP, SOIC and QSOP Packages

Block Diagram

Functional Description

The ASM2P3805AH is a 3.3V, non-inverting clock driver

built using advanced CMOS technology. The device

consists of two banks of drivers, each with a 1:5 fanout and

its own output enable control. The device has a "heartbeat"

monitor for diagnostics and PLL driving. The MON output is

identical to all other outputs and complies with the output

specifications in this document. The ASM2P3805AH offers

low capacitance inputs.

The ASM2P3805AH is designed for high speed clock

distribution where signal quality and skew are critical. The

ASM2P3805AH

also

allows

single

point-to-point

transmission line driving in applications such as address

distribution, where one signal must be distributed to

multiple receivers with low skew and high signal quality.

Pin Diagram

MON

5

5

MON

A

S

M

2

3

8

0

5

A

H

10

11

9

12

8

13

7

14

6

15

5

16

4

17

3

18

2

19

1

20