8 Detailed Description

8.1 Overview

Logic Diagram (Positive Logic) for SN74HCS166 describes the SN74HCS166, an parallel-load 8-bit shift register

with an asynchronous clear ( CLR). These parallel-in or serial-in, serial-out registers feature gated clock (CLK,

CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in modes are established by the

shift/load (SH/ LD) input. When high, SH/ LD enables the serial (SER) data input and couples the eight flip-flops

for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and

synchronous loading occurs on the next clock pulse.

During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of

CLK through a 2-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit

function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input.

This allows the system clock to be free running, and the register can be stopped on command with the other

clock input. CLK INH should be changed to the high level only when CLK is high.

CLR overrides all other inputs, including CLK, and resets all flip-flops to zero. All inputs include Schmitt-triggers

allowing for slow input transitions and providing more noise margin.

8.2 Functional Block Diagram

SH/LD

SER

CLK INH

CLK

C1

1D

R

1

15

2

10

A

B

C

D

E

F

G

H

11

12

13

14

15

16

17

18

CLR

1

C1

1D

R

C1

1D

R

C1

1D

R

C1

1D

R

C1

1D

R

C1

1D

R

C1

1D

R

13

Figure 8-1. Logic Diagram (Positive Logic) for SN74HCS166

8.3 Feature Description

8.3.1 Balanced CMOS Push-Pull Outputs

This device includes balanced CMOS push-pull outputs. The term "balanced" indicates that the device can sink

and source similar currents. The drive capability of this device may create fast edges into light loads so routing

and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable

of driving larger currents than the device can sustain without being damaged. It is important for the output power

of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the

Absolute Maximum Ratings must be followed at all times.

Unused push-pull CMOS outputs should be left disconnected.

8.3.2 CMOS Schmitt-Trigger Inputs

This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are

typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table

from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the

SN74HCS166

SCLS843 – AUGUST 2020

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