PMC271 datasheet(37/90 Pages) PADAUK

37 / 90 page

PMC271/PMS271 Series

8-bit ADC FPPA

TM 8-bit Controller

Page 37 of 90

PDK-DS-PMX271-EN_V105 – Dec. 18, 2018

whenever stating the system. The program code for IHRC frequency calibration is executed only one time that

occurs in writing the codes into OTP memory; after then, it will not be executed again. If the different option for

IHRC calibration is chosen, the system status is also different after boot. The following shows the status of

PMC271/PMS271 for different option:

(1) .ADJUST_IC

SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V, Bandgap=On

After boot up, CLKMD = 0x34：

 IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is enabled

 System CLK = IHRC/2 = 8MHz

 Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode, BG=1.2V

(2) .ADJUST_IC

SYSCLK=IHRC/4, IHRC=16MHz, VDD=3.3V, Bandgap=On

After boot up, CLKMD = 0x14：

 IHRC frequency is calibrated to 16MHz@VDD=3.3V and IHRC module is enabled

 System CLK = IHRC/4 = 4MHz

 Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode, BG=1.2V

(3) .ADJUST_IC

SYSCLK=IHRC/8, IHRC=16MHz, VDD=2.5V, Bandgap=On

After boot up, CLKMD = 0x3C：

 IHRC frequency is calibrated to 16MHz@VDD=2.5V and IHRC module is enabled

 System CLK = IHRC/8 = 2MHz

 Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode, BG=1.2V

(4) .ADJUST_IC

SYSCLK=IHRC/16, IHRC=16MHz, VDD=2.5V, Bandgap=On

After boot up, CLKMD = 0x1C：

 IHRC frequency is calibrated to 16MHz@VDD=2.5V and IHRC module is enabled

 System CLK = IHRC/16 = 1MHz

 Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode, BG=1.2V

(5) .ADJUST_IC

SYSCLK=IHRC/32, IHRC=16MHz, VDD=5V, Bandgap=Off

After boot up, CLKMD = 0x7C：

 IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is enabled

 System CLK = IHRC/32 = 500KHz

 Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode

(6) .ADJUST_IC

SYSCLK=ILRC, IHRC=16MHz, VDD=5V, Bandgap=Off

After boot up, CLKMD = 0XE4：

 IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is disabled

 System CLK = ILRC

 Watchdog timer is disabled, ILRC is enabled, PA5 is input mode

(7) .ADJUST_IC

DISABLE

After boot up, CLKMD is not changed (Do nothing)：

 IHRC is not calibrated and IHRC module is disabled. Bandgap is not calibrated

 System CLK = ILRC

 Watchdog timer is enabled, ILRC is enabled, PA5 is in input mode

PMC271 Datasheet(PDF) 37 Page - PADAUK Technology.

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