PMS15A datasheet(21/68 Pages) PADAUK

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PMS15A/PMS150C Family

8 bit OTP Type IO Controller

Page 21 of 68

PDK-DS-PMS15A/PMS150C-EN-V108 – Jul. 24, 2020

5. Functional Description

5.1. Program Memory – OTP

The OTP (One Time Programmable) program memory is used to store the program instructions to be

executed. The OTP program memory may contains the data, tables and interrupt entry. After reset, the initial

address for FPP0 is 0x000. The interrupt entry is 0x010 if used, the last 16 addresses are reserved for system

using, like checksum, serial number, etc. The OTP program memory for PMS15A/PMS150C is 0.5KW/1KW

that is partitioned as Table 1. The OTP memory from address 0x3F0 to 0x3FF is for system using, address

space from 0x001 to 0x00F and from 0x011 to 0x3EF is user program space.

Address

Function

0x000

FPP0 reset – goto instruction

0x001

User program

•

0x00F

User program

0x010

Interrupt entry address

0x011

User program

•

0x1FF

User program

0x200

User program

•

• ( Not for PMS15A )

0x3EF

User program

0x3F0

System Using

•

0x3FF

System Using

Table 1: Program Memory Organization

5.2. Boot Procedure

POR (Power-On-Reset) is used to reset PMS15A/PMS150C when power up, the boot up time can be optional

fast or slow, time for fast boot-up is about 32 ILRC clock cycles and 2048 ILRC clock cycles for slow boot-up.

Customer must ensure the stability of supply voltage after power up no matter which option is chosen, the

power up sequence is shown in the Fig. 1 and tSBP is the boot-up time.

Please noted, during Power-On-Reset, the VDD must go higher than VPOR to boot-up the MCU.

Fig. 1: Power Up Sequence

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