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Serial

Interface

and

Control

10-Bit

DAC B

Latch

SCLK

DIN

CS

OUTA

Power-On

Reset

x2

10

2-Bit

Control

Latch

Power

and Speed

Control

2

Voltage

Bandgap

PGA With

Output Enable

10-Bit

DAC A

Latch

10

REF

AGND

2

10

10

OUTB

x2

Buffer

10

TLV5637

SLAS224C – JUNE 1999 – REVISED JUNE 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

FUNCTIONAL BLOCK DIAGRAM

Terminal Functions

TERMINAL

I/O/P

DESCRIPTION

NAME

NO.

AGND

5

P

Ground

CS

3

I

Chip select. Digital input active low, used to enable/disable inputs

DIN

1

I

Digital serial data input

OUTA

4

I

DAC A analog voltage output

OUTB

7

O

DAC B analog voltage output

REF

6

I/O

Analog reference voltage input/output

SCLK

2

I

Digital serial clock input

8

P

Positive power supply

2

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