LP5907 datasheet(18/47 Pages) TI

18 / 47 page

GND

OUT

N/C

CIN

COUT

VIN

GND

Enable

VOUT

GND

LP5907

SNVS798O – APRIL 2012 – REVISED JUNE 2020

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10 Layout

10.1 Layout Guidelines

The dynamic performance of the LP5907 is dependant on the layout of the PCB. PCB layout practices that are

adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5907.

Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5907, and as

close to the package as is practical. The ground connections for CIN and COUT must be back to the LP5907

ground pin using as wide and short a copper trace as is practical.

Connections using long trace lengths, narrow trace widths, and/or connections through vias must be avoided.

These add parasitic inductances and resistance that results in inferior performance especially during transient

conditions

10.1.1 X2SON Mounting

The X2SON package thermal pad must be soldered to the printed circuit board for proper thermal and

mechanical performance. For more information, see the QFN/SON PCB Attachment application report.

10.1.2 DSBGA Mounting

The DSBGA package requires specific mounting techniques, which are detailed in AN-1112 DSBGA Wafer Level

Chip Scale Package. For best results during assembly, alignment ordinals on the PC board may be used to

facilitate placement of the DSBGA device.

10.1.3 DSBGA Light Sensitivity

Exposing the DSBGA device to direct light may cause incorrect operation of the device. Light sources such as

halogen lamps can affect electrical performance if they are situated in proximity to the device. Light with

wavelengths in the red and infrared part of the spectrum have the most detrimental effect; thus, the fluorescent

lighting used inside most buildings has very little effect on performance.

10.2 Layout Examples

Figure 24. LP5907MF-x.x (SOT-23) Typical Layout

LP5907 Datasheet(PDF) 18 Page - Texas Instruments