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MCP3551-E/MS Datasheet(PDF) 19 Page - Microchip Technology |
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MCP3551-E/MS Datasheet(HTML) 19 Page - Microchip Technology |
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19 / 30 page ![]() © 2005 Microchip Technology Inc. DS21950B-page 19 MCP3551/3 If 24 bits of data are required from this conversion, they must be accessed during this communication. You can terminate data transition by bringing CS high, but the remaining data will be lost and the converter will go into Shutdown mode. Once the data has been transmitted by the converter, the SDO/RDY pin will remain in the LSB state until the 25th falling edge of SCK. At this point, SDO/RDY is released from the Data Acquisition mode and changed to the RDY state. 5.4.2 2-WIRE CONTINUOUS CONVERSION OPERATION, (CS TIED PERMANENTLY LOW) It is possible to use only two wires to communicate with the MCP3551/3 devices. In this state, the device is always in Continuous Conversion mode, with internal conversions continuously occurring. This mode can be entered by having CS low during power-up or changing it to a low position after power-up. If CS is low at power-up, the first conversion of the converter is initiated approximately 300 µs after the power supply has stabilized. 5.5 Using The MCP3551/3 with Microcontroller (MCU) SPI™ Ports It is required that the microcontroller SPI port be config- ured to clock out data on the falling edge of clock and latch data in on the rising edge. Figure 5-6 depicts the operation shown in SPI mode 1,1 which requires that the SCK from the MCU idles in the High state, while Figure 5-7 shows the similar case of SPI Mode 0,0 where the clock idles in the Low state. The waveforms in the figures are examples of an MCU operating the SPI port in 8-bit mode, and the MCP3551/3 devices do not require data in 8-bit groups. In SPI mode 1,1, data is read using only 24 clocks or three byte transfers. The data ready bit must be read by testing the SDO/RDY line prior to a falling edge of the clock. In SPI mode 0,0, data is read using 25 clocks or four byte transfers. Please note that the data ready bit is included in the transfer as the first bit in this mode. FIGURE 5-6: SPI™ Communication – Mode 1,1. Note: The RDY state is not latched to CS in this mode; the RDY flag dynamically updates on the SDO/RDY pin and remains in this state until data is clocked out using the SCK pin. CS SCK SDO/RDY MCU Data stored into MCU receive register after transmission of first byte Receive Buffer Data stored into MCU receive register after transmission of second byte Data stored into MCU receive register after transmission of third byte DO O 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 543 2 1 0 OL OH 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76 5 4 3 2 1 0 RH L |
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