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PCF8536AT Datasheet(PDF) 26 Page - NXP Semiconductors |
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PCF8536AT Datasheet(HTML) 26 Page - NXP Semiconductors |
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26 / 54 page ![]() PCA85276 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved. Product data sheet Rev. 3 — 12 November 2018 26 of 54 NXP Semiconductors PCA85276 Automotive 40 x 4 LCD driver 7. Characteristics of the I2C-bus The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 7.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time is interpreted as a control signal (see Figure 16). 7.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition - S. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition - P. The START and STOP conditions are illustrated in Figure 17. 7.3 System configuration A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves. The system configuration is shown in Figure 18. Fig 16. Bit transfer Fig 17. Definition of START and STOP conditions |
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