LT3486 datasheet(18/26 Pages) AD

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LT3756/LT3756-1/LT3756-2

Rev. C

For more information www.analog.com

APPLICATIONS INFORMATION

Loop Compensation

TheLT3756usesaninternaltransconductanceerrorampli-

fier whose VC output compensates the control loop. The

external inductor, output capacitor and the compensation

resistor and capacitor determine the loop stability.

The inductor and output capacitor are chosen based on

performance, size and cost. The compensation resistor

and capacitor at VC are selected to optimize control loop

response and stability. For typical LED applications, a

2.2nF compensation capacitor at VC is adequate, and

a series resistor should always be used to increase the

slew rate on the VC pin to maintain tighter regulation of

LED current during fast transients on the input supply to

the converter.

Board Layout

The high speed operation of the LT3756 demands careful

attention to board layout and component placement. The

exposed pad of the package is the only GND terminal of

the IC and is also important for thermal management of

the IC. It is crucial to achieve a good electrical and thermal

contact between the exposed pad and the ground plane of

theboard.Toreduceelectromagneticinterference(EMI),it

isimportanttominimizetheareaofthehighdV/dtswitching

node between the inductor, switch drain and anode of the

Schottky rectifier. Use a ground plane under the switching

node to eliminate interplane coupling to sensitive signals.

The lengths of the high dI/dt traces: 1) from the switch

node through the switch and sense resistor to GND, and

2) from the switch node through the Schottky rectifier and

filter capacitor to GND should be minimized. The ground

points of these two switching current traces should come

to a common point then connect to the ground plane under

the LT3756. Likewise, the ground terminal of the bypass

capacitor for the INTVCC regulator should be placed near

the GND of the switching path. Typically, this requirement

will result in the external switch being closest to the IC,

along with the INTVCC bypass capacitor. The ground for

the compensation network and other DC control signals

should be star connected to the underside of the IC. Do

not extensively route high impedance signals such as FB

and VC, as they may pick up switching noise. In particular,

avoid routing FB and PWMOUT in parallel for more than a

fewmillimetersontheboard.Likewise,minimizeresistance

in series with the SENSE input to avoid changes (most

likely reduction) to the switch current limit threshold.

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