LTC3261 datasheet(8/20 Pages) AD

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LTC3246

3246fa

For more information www.linear.com/LTC3246

PIN FUNCTIONS

WT (Pin 1): Watchdog Timer Control Pin. Attach an ex-

ternal capacitor (CWT) to GND to set a watchdog upper

boundary timeout time (See “Watchdog Timeout Period

vs WT Capacitance” graph on page 6). Tie WT to BIAS to

generate a timeout of about 1.6s. Tie WT and WDI to GND

to disable the watchdog timer.

RT (Pin 2): Reset Timeout Control Pin. Attach an external

capacitor (CRT) to GND to set a reset timeout time (See

“Reset Timeout Period vs RT Capacitance” graph on

page 6). Tie RT to BIAS to generate a reset timeout of

about 200ms.

RSTI (Pin 3): Reset Logic Comparator Pin. The RSTI input

iscomparedtoareferencethreshold(1.2Vtypical).IfRSTI

is below the reference voltage, the part will enter the reset

state and the RST pin will be low. Once RSTI exceeds the

reference voltage and VOUT in regulation, the reset timer

is started. RST pin will be low until the reset period times

out. RSTI is a high impedance pin and must be driven to

a valid level. Do not float.

BIAS (Pin 4, 8): Internal BIAS Voltage. The bias pin is for

internal operation only and should not be loaded or driven

externally. Bypass BIAS with a 10µF or greater ceramic

capacitor.

SEL2 (Pin 5): Logic Input Pin. See Table 1 for SEL1/SEL2

operating logic. SEL2 enables and disables the charge

pump along with the SEL1 pin. The SEL2 pin has a 1µA

(typical) pull down current to ground and can tolerate 38V

inputs allowing it to be pin-strapped to VIN.

VIN(Pin6,9):PowerInputPin.Inputvoltageforbothcharge

pump and IC control circuitry. The VIN pin operates from

2.7V to 38V. All VIN pins should be connected together at

pinsandbypassedwitha1µForgreaterceramiccapacitor.

SEL1 (Pin 7): Logic Input Pin. See Table 1 for SEL1/SEL2

operating logic. SEL1 enables and disables the charge

pump along with the SEL2 pin. The SEL1 pin has a 1µA

(typical) pull down current to ground and can tolerate 38V

inputs allowing it to be pin-strapped to VIN.

Table 1. VOUT Operating Modes

SEL2

SEL1

MODE

LOW

Shutdown

LOW

HIGH

Adjustable VOUT

HIGH

LOW

Fixed 5V

HIGH

Fixed 3.3V

WDI (Pin 10): Watchdog Logic Input Pin. If the watchdog

timer is not disabled then WDI must be driven such that a

falling edge occurs within a time less than the watchdog

upper boundary time, or RST will be asserted low. The

WDI period must also be greater than the watchdog lower

boundary time, and only falling edges are considered. Tie

WT and WDI to GND to disable the watchdog timer. WDI

is a high impedance pin and must be driven to a valid

level. Do not float.

C+ (Pin 11): Connect to positive flying capacitor terminal

only. Do not load or drive externally.

VOUT (Pin 12): Charge Pump Output Voltage. The charge

pumpoutputisenabledifeitherSEL1orSEL2arelogichigh.

C- (Pin 13): Connect to negative flying capacitor terminal

only. Do not load or drive externally.

RST (Pin 14): Reset Open Drain Logic Output. The RST pin

is low impedance during the reset period, and goes high

impedance during the watchdog period. RST is intended

to be pulled up to low voltage supply (such as VOUT) with

an external resistor.

GND (Pin 15, Exposed Pad): Ground. The exposed pack-

age pad is ground and must be soldered to the PC board

ground plane for proper functionality and for rated thermal

performance.

OUTS/ADJ (Pin 16): VOUTSense/AdjustInputPin.Thispin

acts as VOUT sense (OUTS) for 5V or 3.3V fixed outputs

and adjust (ADJ) for adjustable output through external

feedback. The ADJ pin servos to 1.1V when the device is

enabled in adjustable mode. (OUTS/ADJ are selected by

SEL1 and SEL2 pins; See Table 1). Connect OUTS/ADJ to

VOUT or external divider as appropriate.

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