74LS195 datasheet(3/8 Pages) ONSEMI

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SN74LS195A

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LOGIC DIAGRAM

JP0

VCC = PIN 16

GND = PIN 8

= PIN NUMBERS

FUNCTIONAL DESCRIPTION

The Logic Diagram and Truth Table indicate the

functional characteristics of the LS195A 4-Bit Shift

counting and storage applications. It performs serial,

parallel, serial to parallel, or parallel to serial data transfers

at very high speeds.

The LS195A has two primary modes of operation, shift

right (Q0

³ Q1) and parallel load which are controlled by the

state of the Parallel Enable (PE) input. When the PE input is

HIGH, serial data enters the first flip-flop Q0 via the J and

K inputs and is shifted one bit in the direction Q0

³ Q1 ³

³ Q3 following each LOW to HIGH clock transition.

The JK inputs provide the flexibility of the JK type input for

special applications, and the simple D type input for general

applications by tying the two pins together. When the PE

input is LOW, the LS195A appears as four common clocked

D flip-flops. The data on the parallel inputs P0, P1, P2, P3 is

transferred to the respective Q0, Q1, Q2, Q3 outputs

following the LOW to HIGH clock transition. Shift left

operations (Q3

³ Q2) can be achieved by tying the Qn

Outputs to the Pn–1 inputs and holding the PE input LOW.

All serial and parallel data transfers are synchronous,

occurring after each LOW to HIGH clock transition. Since

the LS195A utilizes edge-triggering, there is no restriction

on the activity of the J, K, Pn and PE inputs for logic

operation — except for the set-up and release time

requirements.

A LOW on the asynchronous Master Reset (MR) input

sets all Q outputs LOW, independent of any other input

condition.

MODE SELECT — TRUTH TABLE

OPERATING MODES

INPUTS

OUTPUTS

OPERATING MODES

Asynchronous Reset

Shift, Set First Stage

Shift, Reset First

Shift, Toggle First Stage

Shift, Retain First Stage

Parallel Load

L = LOW voltage levels

H = HIGH voltage levels

X = Don’t Care

I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition.

h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition.

pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to

HIGH clock transition.

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