SN74LS273

http://onsemi.com

4

1.3 V

*The shaded areas indicate when the input is permitted to

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

CP

D

1/f max

MR

CP

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

*

Figure 1. Clock to Output Delays, Clock Pulse Width,

Frequency, Setup and Hold Times Data to Clock

Figure 2. Master Reset to Output Delay, Master Reset

Pulse Width, and Master Reset Recovery Time

AC WAVEFORMS

DEFINITION OF TERMS

required for the correct logic level to be present at the logic

input prior to the clock transition from LOW-to-HIGH in

order to be recognized and transferred to the outputs.

following the clock transition from LOW-to-HIGH that the

logic level must be maintained at the input in order to ensure

continued recognition. A negative HOLD TIME indicates

that the correct logic level may be released prior to the clock

transition from LOW-to-HIGH and still be recognized.

required between the end of the reset pulse and the clock

transition from LOW-to-HIGH in order to recognize and

transfer HIGH data to the Q outputs.