SN74LS373, SN74LS374

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4

Limits

LS373

LS374

Symbol

Parameter

Min

Typ

Max

Min

Typ

Max

Unit

Test Conditions

fMAX

Maximum Clock Frequency

35

50

MHz

tPLH

tPHL

Propagation Delay,

Data to Output

12

12

18

18

ns

CL =45 pF

tPLH

tPHL

Clock or Enable

to Output

20

18

30

30

15

19

28

28

ns

CL = 45 pF,

RL = 667 Ω

tPZH

tPZL

Output Enable Time

15

25

28

36

20

21

28

28

ns

tPHZ

tPLZ

Output Disable Time

12

15

20

25

12

15

20

25

ns

CL = 5.0 pF

Limits

LS373

LS374

Symbol

Parameter

Min

Max

Min

Max

Unit

tW

Clock Pulse Width

15

15

ns

ts

Setup Time

5.0

20

ns

th

Hold Time

20

0

ns

DEFINITION OF TERMS

SETUP TIME (ts) — is defined as the minimum time

required for the correct logic level to be present at the logic

input prior to LE transition from HIGH-to-LOW in order to

be recognized and transferred to the outputs.

HOLD TIME (th) — is defined as the minimum time

following the LE transition from HIGH-to-LOW that the

logic level must be maintained at the input in order to ensure

continued recognition.

SN74LS373

AC WAVEFORMS

Figure 1.

tW

tW

LE

1.3 V

OUTPUT

Dn

ts

th

tPLH

tPHL

Figure 2.

Figure 3.

1.3 V

1.3 V

1.3 V

OE

VOUT

OE

VOUT

tPHZ

1.3 V

1.3 V

tPZL

tPLZ

VOL

1.3 V

VOH

0.5 V

tPZH

1.3 V

1.3 V

0.5 V