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TPS709 Datasheet(PDF) 16 Page - Texas Instruments |
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TPS709 Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 39 page ![]() Channel 4 (50 mA / div) Channel 2 (200 mV / div) Time (500 s / div) m Channel 2 = V Channel 4 = I V = 4.3 V OUT OUT IN G027 Channel 2 (1 V / div) Channel 1 (500 mV / div) Time (50 s / div) m G032 Channel 1 = EN 2 = V V = 4.3 V C = 2.2 F TPS70933 Channel OUT IN OUT m TPS709 SBVS186G – MARCH 2012 – REVISED NOVEMBER 2015 www.ti.com 8.2.2 Detailed Design Procedure Select a 2.2-µF, 10-V X7R output capacitor to satisfy the minimum output capacitance requirement with a 3.3-V dc bias. Select a 1.0-µF, 25-V X7R input capacitor to provide input noise filtering and eliminate high-frequency voltage transients. 8.2.3 Application Curves Figure 37. TPS70933 Load Transient (50 mA to 150 mA) Figure 38. Power-Up with Enable 9 Power Supply Recommendations This device is designed to operate with an input supply range of 2.7 V to 30 V. If the input supply is noisy, additional input capacitors with low ESR can help improve output noise performance. 9.1 Power Dissipation The ability to remove heat from the die is different for each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to ambient air. Performance data for JEDEC low and high-K boards are given in the Thermal Information table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PDISS) is equal to the product of the output current and the voltage drop across the output pass element, as shown in Equation 1: PDISS = (VIN – VOUT) × IOUT (1) 16 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS709 |
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