| Electronic Components Datasheet Search |
|
SN74HCS137 Datasheet(PDF) 14 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
SN74HCS137 Datasheet(HTML) 14 Page - Texas Instruments |
|
14 / 23 page ![]() 2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure optimal performance. This can be accomplished by providing short, appropriately sized traces from the SN74HCS137-Q1 to the receiving device(s). 3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load measured in megaohms; much larger than the minimum calculated above. 4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation. 9.2.3 Application Curve A[2:0] Y[7:0] G0 LE b000 0xFF 0xFB b010 b111 0x7F b001 0xFD b101 b100 0xEF 0xFF Figure 9-2. Application timing diagram SN74HCS137-Q1 SCLS810 – JULY 2020 www.ti.com 14 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: SN74HCS137-Q1 |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |