XRT86L30 datasheet(73/284 Pages) EXAR

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XRT86L30

SINGLE T1/E1/J1 FRAMER/LIU COMBO

PRELIMINARY

REV. P1.0.1

TABLE 47: RECEIVE INTERFACE CONTROL REGISTER (RICR) - E1 MODE

RECEIVE INTERFACE CONTROL REGISTER (RICR)

0X0122

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

RxSyncFrD

R/W

Rx synchronous fractional data interface

0 = Fractional data is clocked out from the chip using RxChCLK

1 = RxChClk is used to output fractional data enable instead of being fraction data

clock. In this mode, fractional data is clocked out of the chip using RxSerClk

(ungapped). RxChn still indicates the time slot number if RxFr2048 is not 1, RxI-

MODE[1:0] = 0, and RxMUXEN = 0.

Reserved

RxPLClkEnb/

R/W

Rx Payload Clock Enable

1 = RxSerClk outputs Rx clock with OH bit period blocked while in 2.048MHz clock

output mode.

RxSyncislow

RxSync is low

In H.100 and HMVIP Mode

1 = RxSync active low.

0 = RxSync active high.

RxFr2048

R/W

Clock Inversion

1 = RxChn[0]/RxSig outputs signaling information, RxChn[1]/RxFrTD will output

fractional channel data in 2.048 MHz mode and RxChn[2] will output the serial

channel number of each time slot.

0 = RxChn[4:0] outputs the parallel channel number as usual.

RxICLKINV

N/A

Clock Inversion

0 = Data transition happens on the rising edge of the transmit clocks.

1 = Data transition happens on the falling edge of the transmit clocks.

RxMUXEN

R/W

Mux Enable

0 = No channel Multiplexing.

1 = Four channels are multiplexed in single serial stream.

RxIMODE[1]

R/W

Rx Intf Mode Selection

This mode selection determines the interface speed.

When RxMUXEN = 0

00 = Receive interface is presenting data at a rate of 2.048Mbit/s.

01 = Receive interface is presenting data at a rate of 2.048Mbit/s.

10 = Receive interface is presenting data at a rate of 4.096Mbit/s.

11 = Receive interface is presenting data at a rate of 8.192Mbit/s.

When RxMUXEN = 1

00 = Reserved

01 = Receive interface is taking data from the four LIU input channels 0 through 3 and

byte-multiplexing into the serial output channel 0. The TxSYNC pulse remains

“High” during the framing bit of each E1 frame.

10 = Receive interface is taking data from the four LIU input channels 0 through 3 and

byte-multiplexing into the serial output channel 0 (HMVIP Mode). The TxSYNC

pulse remains “High” during the last two bits of the previous E1 frame and the first

two bits of the current E1 frame.

11 = Receive interface is taking data from the four LIU input channels 0 through 3 and

byte-multiplexing into the serial output channel 0 (H.100 Mode). The TxSYNC

pulse remains “High” during the last bit of the previous E1 frame and the first bit of

the current E1 frame.

NOTE: Channels 4 through 7 are multiplexed into the serial output at channel 4.

RxIMODE[0]

R/W

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