 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
UPSD3200 Datasheet(PDF) 2 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
UPSD3200 Datasheet(HTML) 2 Page - STMicroelectronics |
|
|
2 / 8 page  µPSD3200 FAMILY 2/8 SUMMARY DESCRIPTION s Dual bank Flash memories – Concurrent operation, read from memory one while erasing and writing the other. In-Appli- cation Programming (IAP) for remote updates – Large 128 KByte or 256 KByte main Flash memory for application code, operating sys- tems, or bit maps for graphic user interfaces – Large 32 KByte secondary Flash memory di- vided in small sectors. Eliminate external EE- PROM with software EEPROM emulation – Secondary Flash memory is large enough for sophisticated communication protocol (USB) during IAP while continuing critical system tasks s Large SRAM with battery back-up option – 8 KByte SRAM for RTOS, high-level languag- es, communication buffers, and stacks s Programmable Decode PLD for flexible address mapping of all memories – Place individual Flash and SRAM sectors on any address boundary – Built-in page register breaks restrictive 8032 limit of 64 KByte address space – Special register swaps Flash memory seg- ments between 8032 “program” space and “data” space for efficient In-Application Pro- gramming s High-speed clock standard 8032 core (12-cycle) – 40 MHz operation at 5 V, 24 MHz at 3.3 V – Two UARTs with independent baud rate, three 16-bit Timer/Counters and two External Interrupts s USB Interface ( µPSD3234A-40U6 only) – Supports USB 1.1 Slow Mode (1.5 Mbit/s) – Control endpoint 0 and interrupt endpoints 1 and 2 s I2C interface for peripheral connections – Capable of master or slave operation s Five Pulse Width Modulator (PWM) channels – Four 8-bit PWM units – One 16-bit PWM unit s Standalone Display Data Channel (DDC) – For use in monitor, projector, and TV applica- tions – Compliant with VESA standards DDC1 and DDC2B – Eliminate external DDC PROM s Six I/O ports with up to 50 I/O pins – Multifunction I/O: GPIO, DDC, I2C, PWM, PLD I/O, supervisor, and JTAG – Eliminates need for external latches and logic s 3000 gate PLD with 16 macrocells – Create glue logic, state machines, delays, etc. – Eliminate external PALs, PLDs, and 74HCxx – Simple PSDsoft Express software ...Free s Supervisor functions – Generates reset upon low voltage or watch- dog time-out. Eliminate external supervisor device – Reset In pin s In-System Programming (ISP) via JTAG – Program entire chip in 10 - 25 seconds with no involvement of 8032 – Allows efficient manufacturing, easy product testing, and Just-In-Time inventory – Eliminate sockets and pre-programmed parts – Program with FlashLINKTM cable and any PC s Content Security – Programmable Security Bit blocks access of device programmers and readers s Zero-Power Technology – Memories and PLD automatically reach standby current between input changes s Packages – 52-pin TQFP – 80-pin TQFP: allows access to 8032 address/ data/control signals for connecting to external peripherals |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
