CY25560
Document #: 38-07425 Rev. *D
Page 2 of 8
General Description
The Cypress CY25560 is a Spread Spectrum Clock Generator
(SSCG) IC used for the purpose of reducing EMI found in
today’s high-speed digital electronic systems.
The CY25560 uses a Cypress proprietary phase-locked loop
(PLL) and Spread Spectrum Clock (SSC) technology to
synthesize and frequency modulate the input frequency of the
reference clock. By frequency modulating the clock, the
measured EMI at the fundamental and harmonic frequencies
of Clock (SSCLK) is greatly reduced.
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory requirements and time to
market without degrading the system performance.
The CY25560 is a very simple and versatile device to use. The
frequency and spread% range is selected by programming S0
and S1 digital inputs. These inputs use three (3) logic states
including High (H), Low (L) and Middle (M) logic levels to select
one of the nine available Spread% ranges. Refer to Table 1 for
programming details.
The CY25560 is optimized for SVGA (40-MHz) and XVGA
(65-MHz) Controller clocks and also suitable for the applica-
tions where the frequency range is 25 to 100 MHz.
A wide range of digitally selectable spread percentages is
made possible by using three-level (High, Low, and Middle)
logic at the S0 and S1 digital control inputs.
The output spread (frequency modulation) is symmetrically
centered on the input frequency.
Spread Spectrum Clock Control (SSCC) function enables or
disables the frequency spread and is provided for easy
comparison of system performance during EMI testing.
The CY25560 is available in an eight-pin SOIC package with
0
°C to 70°C commercial and –40°C to 85°C Industrial
operating temperature ranges.
Pin Description
Pin Number Pin Name
Type
Pin Description
1Xin/CLK
I
Clock or crystal connection input. Refer to Table 1 for input frequency range selection.
2VDD
P
Positive power supply.
3GND
P
Power supply ground.
4SSCLK
O
Modulated clock output which is the same frequency as the input clock or the crystal
frequency.
5
SSCC
I
Spread Spectrum Clock Control (Enable/Disable) function. SSCG function is enabled
when input is HIGH and disabled when input is LOW. This pin is pulled HIGH internally.
6S1
I
Tri-level logic input control pin used to select input frequency range and spread
percent. Refer to tri-level logic on page 3 for programming details. Pin 6 has internal resistor
divider network to VDD and VSS. Refer to Block Diagram on page 1.
7S0
I
Tri-level logic input control pin used to select input frequency range and spread
percent. Refer to tri-level logic on page 3 for programming details. Pin 7 has internal resistor
divider network to VDD and VSS. Refer to Block Diagram on page 1.
8Xout
O
Oscillator output pin connected to crystal. Leave this pin unconnected if an external
clock is used to drive XIN/CLK input (pin-1).
25 – 50 MHz (LowRange)
Input
Frequency
(MHz)
S1=M
S0=M
(%)
S1=M
S0=0
(%)
S1=1
S0=0
(%)
S1=0
S0=0
(%)
S1=0
S0=M
(%)
25– 35
4.3
3.8
3.4
2.9
2.8
35– 40
3.9
3.5
3.1
2.5
2.4
40– 45
3.7
3.3
2.8
2.4
2.3
45– 50
3.4
3.1
2.6
2.2
2.1
50 – 100 MHz (HighRange)
Input
Frequency
(MHz)
S1=1
S0=M
(%)
S1=0
S0=1
(%)
S1=1
S0=1
(%)
S1=M
S0=1
(%)
50– 60
2.9
2.1
1.5
1.2
60– 70
2.8
2.0
1.4
1.1
70– 80
2.6
1.8
1.3
1.1
80– 100
2.4
1.7
1.2
1.0
Select the
Frequency and
Center Spread %
desiredandthen
set S1, S0 as
indicated.
Select the
Frequency and
Center Spread %
desiredandthen
set S1, S0 as
indicated.
Table 1. Frequency and Spread% Selection (Center Spread)
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