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ZSSC3123AI2T Datasheet(PDF) 32 Page - Renesas Technology Corp |
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ZSSC3123AI2T Datasheet(HTML) 32 Page - Renesas Technology Corp |
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32 / 67 page ![]() ZSSC3123 Datasheet © 2018 Integrated Device Technology, Inc. 32 August 16, 2018 10.4 Status and Diagnostics Status bits (the two MSBs of the fetched high data byte; see Table 16) are provided in I2C and SPI but not in PDM. The status bits are used to indicate the current state of the fetched data. Diagnostic detection is available in I2C, SPI, and PDM. In I2C and SPI diagnostics are reported as a saturated high capacitance and temperature output (see Table 16). In PDM, diagnostics are reported as a railed high output level for both PDM_C (capacitive PDM) and PDM_T (temperature PDM). If a diagnostic value is reported then one or more of the errors shown in Table 18 occurred in normal operation. Configuration EEPROM diagnostics are detected at initial power-up of the ZSSC3123 or a wakeup in Sleep Mode and are permanent diagnostics. All other diagnostics are detected during a measurement cycle and reported in the subsequent data fetch for I2C or SPI or in an output register update for PDM. Table 16. Status Bit Definitions Status Bits (I2C or SPI) PDM Output Definition 00BIN Clipped normal output Valid data: Data that has not been fetched since the last measurement cycle. 01BIN Not applicable Stale data: Data that has already been fetched since the last measurement cycle. Note: If a data fetch is performed before or during the first measurement after power-on reset, then “Stale data” will be returned, but this data is actually invalid since the first measurement has not been completed. 10BIN Not applicable Command Mode: The ZSSC3123 is in Command Mode. 11BIN Not used Not used Table 17. Diagnostic Detection I2C or SPI Output PDM Output Definition Saturated output 3FFFHEX High output (railed) level A diagnostic fault has occurred in normal operation (see the following table). Table 18. Normal Operation Diagnostic Table Diagnostic Type Definition Configuration Error Permanent An EEPROM or RAM parity error occurred in the initial loading of the configuration registers. RAM Parity Error Transient A RAM parity error occurred during a microcontroller instruction in the last measurement cycle. EEPROM Error Transient A double-bit error detection (DED) EEPROM error occurred in the last measurement cycle (see section 10.4.1). Math Warning Transient An internal math overflow has occurred in the last measurement cycle and the output might be invalid. |
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