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TMS320F28030 Datasheet(PDF) 80 Page - Texas Instruments |
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TMS320F28030 Datasheet(HTML) 80 Page - Texas Instruments |
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80 / 167 page  0, Value Digital = V 0 input when £ V V V Voltage Analog Input 4096 Value Digital REFLO REFHI REFLO - - ´ = V input V 0 when REFHI < < 4095, Value Digital = V input when REFHI ³ 0, Value Digital = V 0 input when £ 3.3 V Voltage Analog Input 4096 Value Digital REFLO - ´ = V 3.3 input V 0 when < < 4095, Value Digital = V 3.3 input when ³ 80 TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584N – APRIL 2009 – REVISED JUNE 2020 www.ti.com Submit Documentation Feedback Product Folder Links: TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034 TMS320F28035 Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated 6.9.2.1 Analog-to-Digital Converter (ADC) 6.9.2.1.1 Features The core of the ADC contains a single 12-bit converter fed by two sample-and-hold circuits. The sample- and-hold circuits can be sampled simultaneously or sequentially. These, in turn, are fed by a total of up to 16 analog input channels. The converter can be configured to run with an internal band-gap reference to create true-voltage based conversions or with a pair of external voltage references (VREFHI/VREFLO) to create ratiometric-based conversions. Contrary to previous ADC types, this ADC is not sequencer-based. It is easy for the user to create a series of conversions from a single trigger. However, the basic principle of operation is centered around the configurations of individual conversions, called SOCs, or Start-Of-Conversions. Functions of the ADC module include: • 12-bit ADC core with built-in dual sample-and-hold (S/H) • Simultaneous sampling or sequential sampling modes • Full range analog input: 0 V to 3.3 V fixed, or VREFHI/VREFLO ratiometric. The digital value of the input analog voltage is derived by: – Internal Reference (VREFLO = VSSA. VREFHI must not exceed VDDA when using either internal or external reference modes.) – External Reference (VREFHI/VREFLO connected to external references. VREFHI must not exceed VDDA when using either internal or external reference modes.) • Up to 16-channel, multiplexed inputs • 16 SOCs, configurable for trigger, sample window, and channel • 16 result registers (individually addressable) to store conversion values • Multiple trigger sources – S/W – software immediate start – ePWM 1–7 – GPIO XINT2 – CPU Timers 0/1/2 – ADCINT1/2 • 9 flexible PIE interrupts, can configure interrupt request after any conversion |
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