Advanced CMOS Logic – 74AC00

Rev 1.0

19/02/21

Quad 2-Input NAND Gates in bare die form

Die Size (Unsawn)

1200 x 1200

47 x 47

µm

mils

Minimum Bond Pad Size

120 x 120

4.72 x 4.72

µm

mils

Die Thickness

350 (±20)

13.78 (±0.79)

µm

mils

Top Metal Composition

Al 1%Si 1.1µm

Back Metal Composition

N/A – Bare Si



Outputs Sink/Source 24mA



Low Input Current: 1µA



Outputs directly interface CMOS, NMOS and TTL



Operating Voltage Range: 2V to 6V



CMOS High Noise Immunity



Function compatible with 74HC00 or 74LS00



Full Military Temperature Range.

Features:

Ordering Information

The following part suffixes apply:



No suffix - MIL-STD-883 /2010B Visual Inspection

For High Reliability versions of this product please see

54AC00

Supply Formats:



Default – Die in Waffle Pack (400 per tray capacity)



Sawn Wafer on Tape – On request



Unsawn Wafer – On request



Die Thickness <> 350µm(14 Mils) – On request



Assembled into Ceramic Package – On request

74AC00 provides x4 independent 2-input NAND gates

performing the Boolean function Y = A • B or Y = A + B.

The device is fabricated using a 1.5µm 5V CMOS process

combining high speed LSTTL performance with CMOS low

power. Internal circuitry comprises of 3 stages and includes

buffered output for high noise immunity and stability.

Device inputs are compatible with standard CMOS outputs;

with pull-up resistors, they are compatible with LSTTL

outputs. All inputs are equipped with protection circuits

against static discharge and transient excess voltage.

Description

Die Dimensions in µm (mils)

1200 (47)

Mechanical Specification

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