Quad Port 10/100/1000BASE-T PHY with R/GMII, R/TBI Interfaces

VSC8204

The VSC8204 is a low power, low cost, quad port Gigabit Ethernet PHY. It is ideal for Gigabit Ethernet

Switch applications that require a GMII/MII, RGMII, TBI, or RTBI MAC / Switch interface. Vitesse’s

proprietary DSP technology yields robust performance and low power consumption, supporting

1000BASE-T over unshielded twisted pair (UTP) cable, with more than 5dB of design margin with respect

to all worst-case impairments (NEXT, FEXT, Echo, and system noise sources).

SPECIFICA TIONS:

GENERAL DESCRIPTION:

741 Calle Plano

Camarillo, CA 93012, USA

Tel: +1 805.388.3700

Fax: +1 805.987.5896

www.vitesse.com

Vitesse, ASIC-Friendly, FibreTimer, TimeStream and Snoop Loop are trademarks of Vitesse Semiconductor Corporation.

All other trademarks or registered trademarks mentioned herein are the property of their respective holders. Vitesse

Semiconductor Corporation ("Vitesse") retains the right to make changes to its products or specifications to improve

performance, reliability or manufacturability. All information in this document, including descriptions of features,

functions, performance, technical specifications and availability, is subject to change without notice at any time.

PARAMETER

TYP

UNIT

COMMENTS

<1

W

Steady state power consumption (1000BASE-T mode)

>140

m

Cable link length supported in 1000BASE-T & 100BASE-TX

modes, over Category 5 cable

180

m

Cable link length supported in 10BASE-T mode, over

Category 3 cable

VDDIO

3.3

V

Digital I/O and Analog Core power supply voltage

VDDDIG

1.5

V

Digital and Analog Core power supply voltage

25

MHz

Crystal parallel resonant frequency (+/- 100ppm tolerance)

BLOCK DIAGRAM:

For more information on Vitesse Products visit the Vitesse web site

at www.vitesse.com or contact Vitesse Sales at (800) VITESSE

or sales@vitesse.com

BIASING &

REGULATION

SERIAL LED

INTERFACE

PLL

TEST

MANAGER

MII REGISTERS

AUTO-NEGOTIATION

PCS

DECODER

PCS

ENCODER

TIMING RECOVERY

+

DAC

HYBRID

VGA

ADC

FFE

PMA (DSP Data Pump)

PCS

MDI (Analog Front End)

4

TX FIR

X

4

NC1

NC2

NC3

EC

REF_REXT

REF_FILT

LED_CLK

LED_DATA

REFCLK

PLLMODE

CLK125

TXD[7:0]_n

GTX_CLK_n

TX_ER_n

TX_EN_n

COL_n

CRS_n

RXD[7:0]_n

RX_CLK_n

RX_DV_n

RX_ER_n

GMII

RGMII

TBI

RTBI

PHYADD[4:2]

MDC

MDIO

MDINT#

MODE[1:0]_n

MAC I/F

DUPLEX_n

RESET#

PWDN

SERIAL

MANAGEMENT

INTERFACE

Port 3

Port 2

Port 1

TRELLIS

DECODER

PAM-5 SYMBOL

MAPPER,

SCRAMBLER

PAM-5 SYMBOL

DE-MAPPER,

DESCRAMBLER

TDI

TDO

TMS

TCK

TRST#

TXVP_A_n

TXIP_A_n

TXIN_A_n

TXVN_A_n

TXVP_B_n

TXIP_B_n

TXIN_B_n

TXVN_B_n

TXVP_C_n

TXIP_C_n

TXIN_C_n

TXVN_C_n

TXVP_D_n

TXIP_D_n

TXIN_D_n

TXVN_D_n

Port 0

REG_OUT