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ICS952702 Datasheet(PDF) 7 Page - Integrated Circuit Systems

Part # ICS952702
Description  Programmable Timing Control Hub for K7 System
PDF  17 Pages
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS952702 Datasheet(HTML) 7 Page - Integrated Circuit Systems

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7
Integrated
Circuit
Systems, Inc.
ICS952702
0795D—05/06/05
B4 bit7
B4 bit6
B4 bit5
ZCLK
AGP
PCI
0
0
0
Main PLL
Main PLL
Main PLL
0
0
1
132
66
33
0
1
0
132
75.4
37.7
0
1
1
132
88
44
1
0
0
Main PLL
Main PLL
Main PLL
1
0
1
132
66
33
1
1
0
132
75.4
33
1
1
1
132
88
33
Table 2: Asynchronous Frequency Selection Table
Bit
0
*01
10
11
MSB
12
4
8
0
0
4
100
8
1000
16
1100
32
1
1
3
101
6
1001
12
1101
24
10
10
5
110
10
1010
20
1110
40
11
11
15
111
30
1011
60
1111
120
LSB
Address
Div
Address
Div
Address
Div
Address
Div
Table 3: AGP Divider Ratio Combination Table
Divider (3:2)
I
2C Table: Revision ID & Output Divider Control Register
Bit 7
REV_ID3
R
-
-
0
Bit 6
REV_ID2
R
-
-
0
Bit 5
REV_ID1
R
-
-
0
Bit 4
REV_ID0
R
-
-
1
Bit 3
AGPDiv3
RW
1
Bit 2
AGPDiv2
RW
1
Bit 1
AGPDiv1
RW
0
Bit 0
AGPDiv0
RW
1
AGP divider ratio can be
configured via these 4
bits individually.
See Table 3: Divider Ratio Combination
Table
1PWD
0
Control Function
Name
Type
-
-
-
-
-
-
-
-
Byte 5
Pin #
Revision ID
I
2C Table: Async Frequency Selection & Output Skew Control Register
Bit 7
ASYNC2
RW
0
Bit 6
ASYNC1
RW
0
Bit 5
ASYNC0
RW
0
Bit 4
Reserved
Reserved
RW
-
-
1
Bit 3
ZCLKSkw1
RW
0
Bit 2
ZCLKSkw0
RW
1
Bit 1
AGPSkw1
RW
0
Bit 0
AGPSkw0
RW
1
Fix PLL Async Freq
Programming bits
See Table 2: Async Frequency Selection
Table
1
-
Byte 4
-
-
-
-
-
-
-
Pin #
Name
Type
Control Function
PWD
0
CPU-ZCLK Skew Control
00:0ps; 01:250ps; 10:500ps; 11:750ps
This byte will advance or delay the skew
by 250ps per step
CPU-AGP Skew Control
00:0ps; 01:250ps; 10:500ps; 11:750ps
This byte will advance or delay the skew
by 250ps per step



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