235
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AS998/AS998A
PWM Controller
Pin Function Description
Pin Number Function
Description
1OV
Overvoltage pin. The OV input/output function is implemented by an on-chip latch.
This pin is driven to the Reg voltage if the on-chip circuitry senses a VDD level greater
than the OV threshold (VDDov). This error condition stops the part from generating
any more output pulses until VDD has been reduced to the VDDul level and then
raised as in a normal power-on sequence.
Alternatively, the OV error condition can be cleared by forcing the OV pin to near
ground. The output is immediately enabled following an OV clear function. The OV
error condition can also be generated externally by temporarily forcing the OV pin to a
voltage greater than the VOV threshold. This will force the part to latch an
OV condi-
tion and not generate any more output pulses unless cleared as
described.
2
COMP
Compensation pin. This pin is the output of the error amplifier and can also be used
as an input for an optocoupled control signal to the PWM comparator. Generally this
pin is connected to a feedback network to FB. If an optocoupler feedback is used,
COMP connects to the collector of the common emitter optocoupler, generally with a
pull-up resistor to VDD or Reg.
3FB
Feedback pin. Inverting input to the error amplifier. This pin is tied to an internal
default divider which will tend to regulate VDD at a nominal 11V.
4
CSNS
Current sense input. The signal on this pin is fed via a low pass filter to the PWM
com-parator. Superimposed on the input to the PWM is a slope compensation ramp
derived from the main oscillator.
In addition to the above, the current sense signal is connected directly to an over-
current comparator that detects an overload condition and immediately terminates the
gate drive pulse with a minimum propagation delay.
5GND
Circuit common ground.
6
OUT
Gate drive output. The current source and sink capability of the output buffer is tailor-
ed to minimize EMI. When the IC is not running, this pin is held low so a pull down
resistor on the FET gate is not required.
7
VDD
Positive supply voltage. An on-board shunt regulator allows this IC to be powered via
a simple resistor from a widely varying bias supply.
The ICs power management block keeps the part in startup current mode while VDD
is ramping up until the part turns on at the UVLhigh threshold. The IC then draws the
specified supply current while operating unless VDD drops below the UVLlow thresh-
old. If VDD drops below UVLlow, then the part will return to startup current mode.
8
REG
Voltage regulator. Decoupling pin as required for internal low voltage supply. This pin
may be used to source 1mA for the control optocoupler.
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