STw4141

4 Application information

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4.6.2

Input capacitor (CIN selection)

Input capacitor of 10

µF ceramic low ESR capacitor should be used to reduce switching losses.

It should be placed as close as possible to supply pins VDD and PVDD. The connection traces

should be wide and short to minimize impedance.

4.6.3

Output capacitors (COUT selection)

The selection of COUT is driven by the required ESR to minimize voltage ripple and load step

transients. There are two possibilities for output capacitors: either a 22

µF is connected to

ground or two 10

µF ceramic are used to reduce ESR and switching losses. The capacitor

short to minimize impedance.

4.6.4

Capacitors selection

4.7

PCB layout considerations

The Printed Circuit Board layout must include the following consideration:

Current paths carrying high currents (bold lines in

Figure 15) must be wide and short to

minimize impedance in order to reduce looses and EMI.

Small currents flow through voltage paths. No specific care is requested about voltage paths

but it is recommended to follow the general rules for PCB routing to reduce influence of external

and internal interferences.

Table 10.

Bill of Material: capacitor selection

Component

Supplier

Part number

Value

Case size

C

IN

TDK

C1608X5R0J106MT

10

µF, 6.3V

0603

TDK

C2012X5R0J106MT

10

µF, 6.3V

0805

TAIYO YUDEN

JMK212BJ106MG-T

10

µF, 6.3V

0805

TDK

C1608X5R0J106MT

2 x 10

µF, 6.3V

2 x 0603

C2012X5R0J106MT

2 x 10

µF, 6.3V

2 x 0805

C2012X5R0J226MT

22

µF, 6.3V

0805

TAIYO YUDEN

JMK212BJ106MG-T

2 x 10

µF, 6.3V

2 x 0805

JMK212BJ226MG-T

22

µF, 6.3V

0805