LM4846TL datasheet(9/19 Pages) NSC

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Application Information

2C PIN DESCRIPTION

SDA: This is the serial data input pin.

SCL: This is the clock input pin.

ID_ENB: This is the address select input pin.

2CSPI_SEL: This is tied LOW for I2C mode.

2C COMPATIBLE INTERFACE

The LM4846 uses a serial bus which conforms to the I

protocol to control the chip’s functions with two wires: clock

(SCL) and data (SDA). The clock line is uni-directional. The

data line is bi-directional (open-collector). The maximum

clock frequency specified by the I

2C standard is 400kHz. In

this discussion, the master is the controlling microcontroller

and the slave is the LM4846.

The I

2C address for the LM4846 is determined using the

ID_ENB pin. The LM4846’s two possible I

2C chip addresses

are of the form 111110X

10 (binary), where X1 = 0, if ID_ENB

is logic LOW; and X

1 = 1, if ID_ENB is logic HIGH. If the I

interface is used to address a number of chips in a system,

the LM4846’s chip address can be changed to avoid any

possible address conflicts.

The bus format for the I

2C interface is shown in Figure 3. The

bus format diagram is broken up into six major sections:

The "start" signal is generated by lowering the data signal

while the clock signal is HIGH. The start signal will alert all

devices attached to the I

2C bus to check the incoming ad-

dress against their own address.

The 8-bit chip address is sent next, most significant bit first.

The data is latched in on the rising edge of the clock. Each

address bit must be stable while the clock level is HIGH.

For I

2C interface operation, the I2CSPI_SEL pin needs to be

tied LOW (and tied high for SPI operation).

After the last bit of the address bit is sent, the master

releases the data line HIGH (through a pull-up resistor).

Then the master sends an acknowledge clock pulse. If the

LM4846 has received the address correctly, then it holds the

data line LOW during the clock pulse. If the data line is not

held LOW during the acknowledge clock pulse, then the

master should abort the rest of the data transfer to the

LM4846.

The 8 bits of data are sent next, most significant bit first.

Each data bit should be valid while the clock level is stable

HIGH.

After the data byte is sent, the master must check for another

acknowledge to see if the LM4846 received the data.

If the master has more data bytes to send to the LM4846,

then the master can repeat the previous two steps until all

data bytes have been sent.

The "stop" signal ends the transfer. To signal "stop", the data

signal goes HIGH while the clock signal is HIGH. The data

line should be held HIGH when not in use.

2C INTERFACE POWER SUPPLY PIN (I2CV

DD)

The LM4846’s I

2C interface is powered up through the

2CV

DD pin. The LM4846’s I

2C interface operates at a volt-

age level set by the I

2CV

DD pin which can be set indepen-

dent to that of the main power supply pin V

DD. This is ideal

whenever logic levels for the I

2C interface are dictated by a

microcontroller or microprocessor that is operating at a lower

supply voltage than the main battery of a portable system.

201668F5

FIGURE 3. I

2C Bus Format

LM4846TL Datasheet(PDF) 9 Page - National Semiconductor (TI)

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