LTM4677 datasheet(22/132 Pages) AD

22 / 132 page

LTM4681

Rev. 0

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VTRIM3_CFG (AB9): Output Voltage Select Pin for VOUT3,

Fine Setting. Works in combination with VOUT3_CFG to

affect the VOUT_COMMAND (and associated output volt-

age monitoring and protection/fault-detection thresholds)

of channel 3, at SVIN_23 power-up. (See VOUT3_CFG and

the Applications Information section.) A resistor divider

from 2.5V to SGND connected to the pin will set the TRIM

value. See Table 2. Minimize capacitance especially when

the pin is left open to assure accurate detection of the

pin state. Note that use of RCONFIGs on VOUT3_CFG/

VTRIM3_CFG can affect the VOUT3 range setting (MFR_

PWM_MODE0[1]) and loop gain. For addressed ASEL_23,

Page 0x00 corresponds to channel 2 and Page 0x01 cor-

responds to Channel 3. See PAGE description section.

RUN0, RUN1 (B10, B11 Respectively): Enable Run Input

for Channels 0 and 1, respectively. Open-drain input and

output. Logic high on these pins enables the respective

outputs of the LTM4681. These open-drain output pins

hold the pin low until the LTM4681 is out of reset and

SVIN_01 is detected to exceed VIN_ON. A pull-up resistor

to 3.3V is required in the application. The LTM4681 pulls

RUN0 and/or RUN1 low, as appropriate, when a global

fault and/or channel-specific fault occurs whose fault

response is configured to latch off and cease regulation;

issuing a CLEAR_FAULTS command via I2C or power-

cycling SVIN_01 is necessary to restart the module, in such

cases. Do not pull RUN logic high with a low impedance

source. INTVCC is active when SVIN_01 is above UVLO.

This provides power to the VDD33 and VDD25 to allow

programming the EERROM.

RUN2, RUN3 (Y9, Y8): Enable Run Input for Channels 2

and 3, respectively. Open-drain input and output. Logic

high on these pins enables the respective outputs of the

LTM4681. These open-drain output pins hold the pin low

until the LTM4681 is out of reset and SVIN_23 is detected

to exceed VIN_ON. A pull-up resistor to 3.3V is required in

the application. The LTM4681 pulls RUN2 and/or RUN3

low, as appropriate, when a global fault and/or channel-

specific fault occurs whose fault response is configured to

latch off and cease regulation; issuing a CLEAR_FAULTS

command via I2C or power-cycling SVIN_23 is necessary

to restart the module, in such cases. Do not pull RUN

logic high with a low impedance source. INTVCC is active

when SVIN_23 is above UVLO. This provides power to the

VDD33 and VDD25 to allow programming the EEPROM.

PGOOD0, PGOOD1, PGOOD2, PGOOD3 (H9, H8, R10,

T10): Power Good Indicator Outputs. Open-drain logic

output that is pulled to ground when the output exceeds

the UV and OV regulation window. The output is de-

glitched by an internal 100µs filter. A pull-up resistor to

3.3V is required in the application.

FAULT0, FAULT1, FAULT2, FAULT3 (A11, A10, V10,

W10): Digital Programmable FAULT Inputs and Outputs.

Open-drain output. A pull-up resistor to 3.3V is required

in the application.

COMP0b, COMP1b, COMP2b, COMP3b (G10, F9, T9,

W11): Current Control Threshold and Error Amplifier

Compensation Nodes. Each associated channel’s current

comparator tripping threshold increases with its compen-

sation voltage. Each channel has a 22pF to SGND.

COMP0a, COMP1a, COMP2a, COMP3a (G11, G9, T8,

V11): Loop Compensation Nodes. The internal PWM

loop compensation resistors RCOMPn of the LTM4681

can be adjusted using bit[4:0] of the MFR_PWM_COMP

command. The transconductance of the LTM4681 PWM

error amplifier can be adjusted using bit[7:5] of the MFR_

PWM_COMP command. These two loop compensation

parameters can be programmed when device is in opera-

tion. Refer to the Programmable Loop Compensation sub-

section in the Applications Information section for further

details. See Figure 1.

SYNC_01, SYNC_23 (D11,V9): External Clock

Synchronization Input and Open-Drain Output Pin. If

an external clock is present at this pin, the switching

frequency will be synchronized to the external clock. If

clock master mode is enabled, this pin will pull low at

the switching frequency with a 500ns pulse to ground.

A resistor pull-up to 3.3V is required in the application if

the LTM4681 is the master.

SCL_01, SCL_23 (D10, W9): Serial Bus Clock Open-Drain

Input (Can Be an Input and Output, if Clock Stretching

is Enabled). A pull-up resistor to 3.3V is required in the

PIN FUNCTIONS

LTM4677 Datasheet(PDF) 22 Page - Analog Devices

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