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DSC2121 DSC2221

Page 2

MK-Q-B-P-D-12050104

DSC2121

DSC2221

Pin Description

Pin No.

Pin Name

Pin Type

Description

1

Enable

I

Enables outputs when high and disables when low

2

NC

NA

Leave unconnected or grounded

3

NC

NA

DSC2121: Leave unconnected or grounded

SCLK

I

DSC2221: Serial clock from master

4

GND

Power

Ground

5

SDA

I

MOSI

DSC2221: SPI Serial Data from Master to Slave

6

SCL

I

MISO

O

DSC2221: SPI Serial Data from Slave to Master

7

CS_bar

I

SS

I

DSC2221: SPI Slave Select (Active Low)

8

Output1+

O

Positive LVPECL Output

9

Output1-

O

Negative LVPECL Output

10

NC

NA

Leave unconnected or grounded

11

Output 2+

O

CMOS Output

12

VDD2

Power

Power Supply for CMOS Output

13

VDD

Power

Power Supply

14

FS

I

Default output clock frequency bit

Operational Description

The DSC2121/2221 is a dual LVPECL oscillator

consisting of a MEMS resonator and a support

PLL IC. The outputs are generated through

independent 8-bit programmable dividers from

the output of the internal PLL.

DSC2121/2221 allows for easy programming

interface. Upon power-up, the initial output

frequencies are controlled by an internal pre-

programmed memory (OTP).

This memory

stores all coefficients required by the PLL for

two different default frequency pairs.

The

control pin (FS) selects the initial pair. Once

the device is powered up, a new output

frequency

pair

can

be

programmed.

Programming details are provided in the

Programming

Guide.

Standard

default

frequency pairs are described in the following

sections. Discera supports customer defined

versions of the DSC2121/2221.

When Enable (pin 1) is floated or connected to

VDD, the DSC2121/2221 is in operational

mode. Driving Enable to ground will tri-state

both output drivers (hi-impedance mode).

The DSC2121/2221 has programmable CMOS

output drive strength, which can be controlled

times for the output with a 15pf load

capacitance as a function of these control bits

at VDD=3.3V and room temperature.

Table 1. Rise/Fall times for drive strengths

Output Drive Strength Bits

[OXS2, OXS1, OXS0] - Default [111]

X=1 for output1, and 2 for output2

000 001 010 011 100 101 110 111

2

1.8 1.6 1.3 1.3

VDD2 supply the CMOS output and must be

equal to or less than VDD. VDD2 can be as

low as 1.65V.