PRT2011DAF4A datasheet(111/112 Pages) NXP

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Revision history

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 08/2020

NXP Semiconductors

111

Revision history

Table 89 provides a revision history for this data sheet.

Table 89. i.MX RT1064 Data Sheet document revision history

Rev.

Number

Date

Substantive Change(s)

Rev. 2

08/2020

• Changed the MPCore to core in the Section 1.1, Features

• Added new part numbers in the Table 1, Ordering information

• Updated the Figure 1, "Part number nomenclature—i.MX RT1064"

• Updated the frequency of RTC OSC in the Table 2, i.MX RT1064 modules list

• Updated conditions and maximum current of DCDC_IN in the Table 12, Maximum supply currents

• Added a restrictions in the Section 4.2.1.1, Power-up sequence

• Added IOH and IOL in the Table 22, Single voltage GPIO DC parameters

• Updated the minimum and maximum values in the Table 33, SEMC output timing in SYNC mode

• Updated the VDDAD to VDDA in the Table 54, 12-bit ADC operating conditions and Table 55, 12-bit

ADC characteristics (VREFH = VDDA, VREFL = VSSAD)

Rev. 1

12/2019

• Updated ADC and SPI NAND Flash in the Section 1.1, Features; removed DAC from Section 1.1,

Features

• Updated ADC and RAM in the Figure 2, "i.MX RT1064 system block diagram"

• Updated the RT website link in the Section 1.2, Ordering information

• Updated FlexSPI, LCD/CSI/PXP, and SNVS in the Table 1, Ordering information; added KPP, SPI,

XBAR/AOI, CSU, and second package information in the Table 1, Ordering information

• Removed tamper detection from the Table 2, i.MX RT1064 modules list

• Updated the on-chip termination values of JTAG_TCK and JTAG_MOD in the Table 4, JTAG

Controller interface summary

• Updated the Section 4.1.2, Thermal resistance

• Changed 528 MHz PLL to System PLL in the Table 16, System PLL’s electrical parameters

• Changed 480 MHz PLL to USB PLL in the Table 18, USB PLL’s electrical parameters

• Updated the VDD name of supply voltage conditions column in the Table 54, 12-bit ADC operating

conditions

• Updated the Section 4.9.1, LPSPI timing parameters

• Updated the Table 82, Boot through UART1 and removed the Table, Booth through UART2

• Updated the Figure 53, "10 x 10 mm BGA, case x package top, bottom, and side Views"

• Added the Section 7.2, 12 x 12 mm package information

Rev. 0.1

01/2019

• Removed the word “no” from LCD/CSI/PXP row in the Table 1, Ordering information

• Added the Figure 36, "Minimum Sample Time Vs Ras (Cas = 2 pF)", Figure 37, "Minimum Sample

Time Vs Ras (Cas = 5 pF)", and Figure 38, "Minimum Sample Time Vs Ras (Cas = 10 pF)"

Rev. 0

10/2018

• Initial version

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