www.ti.com

1

2

3

13

12

14

DCP02xU

28

27

26

C

16

R

7

C

17

C

18

R

8

C

20

C

19

VS4

0S4

+V4

COM4

-V4

NC

NC

1

2

3

13

12

14

C

11

R

5

C

13

C

12

R

6

C

14

C

15

VS3

0S3

+V3

COM3

-V3

28

27

26

C

1

R

1

C

3

C

2-1

C

2

R

2

C

5

C

4-1

C

4

VS1

0V1

+V1

COM1

-V1

C

6

R

3

C

8

C

7-1

C

7

R

4

C

10

C

9-1

C

9

VS2

0V2

+V2

COM2

-V2

1

2

6

5

7

1

2

6

5

7

14

14

DCP02xP

SYNC

DCP02xP

SYNC

DCP02xU

SYNC

SYNC

JP1

JP2

JP1

JP2

CON1

CON2

CON3

CON4

(1)CapacitorsC

,C

,C

,andC

arethrough-holeplatedcomponentsconnectedinparallelwithC ,C ,C ,andC (1206SMD),respectively.

(2)Foroptimumlow-noiseperformance,uselow-ESRcapacitors.

(3)DonotconnecttheSYNCpinjumper(JP1−JP4)iftheSYNCfunctionisnotbeingused.

(4)Connectionstothepowerinputshouldbemadewithaminimumwireof16/0.2twistedpair,withthelengthkeptshort.

(5)VSxand0Vxareinputsupplyandgroundrespectively(xrepresentsthechannel).

(6)+Vxand −Vxarethepositiveandnegativeoutputs,referencedtoacommongroundCOMx.

(7)JPxarethelinksusedforself-synchronization;ifthisfacilityisnotbeingused,thelinksshouldbeunconnected.

(8)R1−R8arethepoweroutputloads;donotfittheseifanexternalloadisconnected.

(9)CON1andCON2areDIL-14;CON3andCON4areSO-28packages.

(10)NC=notconnected.

2−1

4−1

7−1

9−1

2

4

7

9

DCP02 Series

SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008

Figure 13. Example of PCB Layout, Schematic Diagram

12

Submit Documentation Feedback

Copyright © 2000–2008, Texas Instruments Incorporated

Product Folder Link(s): DCP02 Series