SP5654SLASHKGSLASHMPAS datasheet(7/15 Pages) ZARLINK

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SP5654

FUNCTIONAL DESCRIPTION

The SP5654 contains all the elements necessary, with the

exception of reference crystal, loop filter and external high

voltage transistor, to control a voltage controlled local

oscillator, so forming a PLL frequency synthesised source.

The system is controlled by a microprocessor via a

standard data, clock and enable three–wire bus. The data load

consists of a single word, which contains the frequency and

port information, and is only transferred to the internal data

shift register during an enable high period. The clock is

disabled during low periods. New data words are only

accepted by the internal data buffers from the shift register on

a negative transition of the enable, so giving improved fine

tuning facility for digital AFC etc.

The device has 5 modes of operation, as defined in Table

1, and each of these modes can accept either 18–bit or 19–bit

data entry. The format of the data entry is shown in Fig. 4, and

consists of 4–bits for port switching, plus 14/15 bits to control

the 15–bit programmable divider. For 18–bit data entry (4+14),

the MSB of the 15–bit programmable divider is internally set to

logic ‘0’ effectively making the divider 14–bits. The device

recognises the data entry as 18–bit when a falling edge at the

enable input occurs during the 18th clock period. The device

associates falling enable edges during the 19th clock period

with 19–bit data entry. A falling edge at the enable input before

the 18th clock period constitutes invalid data entry to the

device.

The frequency is set by first selecting the required mode of

operation as detailed in Table 1, and then by loading the

programmable divider with the required 14/15–bit divisor

word. The output of this divider, FPD, is fed to the phase

comparator where it is compared in phase and frequency to

the internally generated comparison frequency, FCOMP.

The comparison frequency FCOMP is obtained by dividing

the output of the on–chip crystal controlled oscillator. The

crystal frequency generally used is 4MHz, giving an FCOMP of

7.8125kHz in mode 4, which when multiplied back up to the LO

gives a minimum step size of 125kHz.

The programmable divider is preceded by an input RF

preamplifier and high speed low radiation prescaler. The

preamplifier is arranged to be self oscillating, so giving

excellent input sensitivity. The input impedance and sensitivity

are shown in Fig. 2 and 6 respectively.

The device contains a lock detect circuit which generates

a flag when the loop has attained lock. The ‘in lock’ condition

is indicated by a high impedance state.

The charge pump current is initially set to

150mA. When

the device attains frequency lock, the charge pump current is

switched to

50mA, so improving the local oscillator short term

jitter.

The device also contains four general purpose open

collector output ports P0–P3. These outputs are each capable

of sinking a minimum of 10mA, when the appropriate bits

P0–P3 of the programming data, see Fig. 4 are set to a logic

‘1’.

PIN and PROGRAMMING COMPATIBILITY

The SP5654 may be used in SP5655 applications which

require 3–wire bus as opposed to I2C bus data format. In

SP5655 applications where the reference crystal is grounded

to pin 3, a small modification is required to ground the crystal

as shown in Fig. 5.

Appropriate connections must also be to the mode select

input (see Table 1). For each mode of operation, the SP5654

is programming and step size compatible with Toshiba

devices as shown in Table 3.

TEST FEATURES

Charge pump disable

The charge pump may be disabled by sourcing current

from the data input, i.e. by forcing a negative input voltage.

Varactor line disable

The charge pump amplifier drive output may be disabled by

sourcing current from the enable input, i.e. by forcing a

negative voltage.

Device test mode

Further test modes can be invoked by sourcing current

from the clock input, i.e. by forcing a negative input voltage.

These test modes when invoked are determined by the data

held in the P1, P2 and P3 internal registers as detailed in Table

MODE

‘MODE SELECT’

INPUT VOLTAGE

PROGRAMMABLE

DIVIDER BIT

LENGTH

REFERENCE

DIVIDER RATIO

*FREQUENCY

STEP SIZE

(kHz)

*MAXIMUM

OPERATING

FREQUENCY (GHz)

14 bit

15 bit

0.85 VCC – VCC

14/15

512

125

2.0479

2.7000

0.65 VCC – 0.75VCC #

14/15

1280

0.8191

1.6383

OPEN CIRCUIT

14/15

1024

62.5

1.0239

2.0479

0.25 VCC – 0.35VCC [

14/15

2048

31.25

0.5119

1.0239

0 – 0.15 VCC

14/15

640

100

1.6383

2.7000

*When used with a 4MHz crystal

# Selected by connecting a 15k

W resistor to VCC

[ Selected by connecting a 15kW resistor to VEE

Table 1. Modes of operation

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