C9950
Document #: 38-07072 Rev. *C
Page 2 of 7
Note:
2.
PD = Internal Pull-Down, PU = Internal Pull-Up.
Pin Description[2]
Pin
Name
PWR
I/O
Type
Description
8
XIN
I
Oscillator Input. Connect to a crystal.
9
XOUT
0
Oscillator Output. Connect to a crystal.
30
TCLK
I
External Test Clock Input.
28
QA
VDDC
O
Clock Output. See Frequency Table.
26
QB
VDDC
O
Clock Output. See Frequency Table.
22, 24
QC(1,0)
VDDC
O
Clock Outputs. See Frequency Table.
12, 14, 16, 18, 20
QD(4:0)
VDDC
O
Clock Outputs. See Frequency Table.
2
FB_SEL
I
PD
Feedback Select Input.
If FB_SEL = 1, then the (
÷8) counter is selected in the PLL feed-
back loop.
If FB_SEL = 0, then the (
÷16) counter is selected in the PLL
feedback loop.
10
MR/OE#
I
Master Reset/Output Enable Input. When asserted HIGH, resets
all of the internal flip-flops and also disables all of the outputs.
When pulled LOW, releases the internal flip-flops from reset and
enables all of the outputs.
31
PLL_EN
I
PLL Enable Input. When asserted HIGH, PLL is enabled. And
when set LOW, PLL is bypassed.
32
REF_SEL
I
Reference Select Input. When HIGH, TCLK is the reference clock
and when LOW, the crystal oscillator is selected.
3, 4, 5, 6
SEL(A:D)
I
Frequency Select Inputs. See Frequency Table.
If SEL_ = 1, then QA divider =
÷4, QB:D divider = ÷8
If SEL_ = 0, then QA divider =
÷2, QB:D divider = ÷4
11, 15, 19, 23, 27
VDDC
3.3V Power Supply for Output Clock Buffers.
1
VDD
3.3V Power Supply for PLL
7, 13, 17, 21, 25,
29
VSS
Common Ground
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