ADGS5414BCPZ datasheet(25/30 Pages) AD

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Data Sheet

ADGS5414

Rev. 0 | Page 25 of 30

BREAK-BEFORE-MAKE SWITCHING

The ADGS5414 exhibits break-before-make switching action,

which allows the use of the device in multiplexer applications. A

multiplexer function can be achieved by externally hardwiring the

device in the required mux configuration, as shown in Figure 45.

SCLK SDI CS RESET/VL

SPI

INTERFACE

4:1 MUX

4 × SPST

Figure 45. An SPI Controlled Switch Configured in a 4:1 Mux

TRENCH ISOLATION

In the analog switch section of the ADGS5414, an insulating oxide

layer (trench) is placed between the N-type metal-oxide semi-

conductor (NMOS) and the P-type metal-oxide semiconductor

(PMOS) transistors of each complementary metal-oxide semi-

conductor CMOS switch. Parasitic junctions, which occur between

the transistors in junction isolated switches, are eliminated, and

the result is a completely latch-up proof switch.

In junction isolation, the P-well and N-well of the PMOS and

NMOS transistors form a diode that is reverse-biased under

normal operation. However, during overvoltage conditions, this

diode can become forward-biased. A silicon controlled rectifier

(SCR) circuit is formed by the two transistors, causing a significant

amplification of the current that, in turn, leads to latch-up. With

trench isolation, this diode is removed, and the result is a latch-

up proof switch.

The Analog Devices, Inc., high voltage latch-up proof family of

switches and multiplexers provides a robust olution for

instrumentation, industrial, aerospace, and other harsh

environments that are prone to latch-up, which is an

undesirable high current state that can lead to device failure and

persists until the power supply is turned off. The ADGS5414

high voltage switches allow single-supply operation from 9 V to

40 V and dual-supply operation from ±9 V to ±22 V.

NMOS

PMOS

P-WELL

N-WELL

BURIED OXIDE LAYER

HANDLE WAFER

TRENCH

Figure 46. Trench Isolation

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