L6981 datasheet(26/49 Pages) STMICROELECTRONICS

26 / 49 page

VOUT=0.85∙ 1+R1R2

(28)

CR1 capacitor is sometimes useful to increase the small signal phase margin (please refer to Section 7 Closing

the loop)

Figure 29. Application circuit

(*) Synchronization is allowed only for LNM versions.

8.4

Design of the power components

8.4.1

Input capacitor selection

The input capacitor voltage rating must be higher than the maximum input operating voltage of the application.

During the switching activity a pulsed current flows into the input capacitor and so, its RMS current capability must

be selected accordingly with the application conditions. Internal losses of the input filter depend on the ESR value,

so usually low ESR capacitors (like multilayer ceramic capacitors) have higher RMS current capability. On the

other hand, given the RMS current value, lower ESR input filter has lower losses and so contributes to higher

conversion efficiency.

The maximum RMS input current flowing through the capacitor can be calculated as:

IRMS=IOUT∙ 1−Dη ∙Dη

(29)

Where IOUT is the maximum DC output current, D is the duty cycles, η is the efficiency. This function has a

maximum at D = 0.5 and, considering η = 1, it is equal to IOUT/2. In a specific application, the range of possible

duty cycles has to be considered in order to find out the maximum RMS input current. The maximum and

minimum duty cycles can be calculated as:

DMAX= VOUT+∆VLOWSIDE

VINmin+∆VLOWSIDE−∆VHIGHSIDE

(30)

Dmin= VOUT+∆VLOWSIDE

VINMAX+∆VLOWSIDE−∆VHIGHSIDE

(31)

Where ΔVHIGHSIDE and ΔVLOWSIDE are the voltage drops across the embedded switches. The peak-to-peak

voltage across the input filter can be calculated as:

VPP= IOUT

CIN∙FSW∙ 1−Dη ∙Dη+ESR∙ IOUT+∆IL

(32)

In case of negligible ESR (MLCC capacitor), the equation of CIN as a function of the target VPP can be written as

follows:

CIN= IOUT

VPP∙FSW∙ 1−Dη ∙Dη

(33)

L6981

Design of the power components

DS13554 - Rev 1

page 26/49

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