MAX20029BATIDV datasheet(13/17 Pages) MAXIM

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Inductor Selection

The PMICs are optimized for use with a 1.5µH inductor

on outputs configured for 0.5A, 1A, or 1.5A, and a 1.0µH

inductor for an output configured for 2A or 3A. For output

voltageslessthan0.9V,0.47μHisrecommended.

Input Capacitor

The PMICs are designed to operate with a single 2.2µF

ceramic bypass capacitor on each PV_ input. Phase

interleaving of the four buck converters contributes to

a lower required input capacitance by canceling input

ripple currents. Place the bypass capacitors as close as

possible to their corresponding PV_ input to ensure the

best EMI and jitter performance.

Output Capacitor

All outputs of the PMICs are optimized for use with ceramic

capacitors.

For VOUT/VIN > 0.2:

OUT_MIN

OUT

OUT_NOM

OUT

µF

For VOUT/VIN≤0.2:

OUT_MIN

OUT

OUT_NOM

OUT

µF

Additional output capacitance can be used if better volt-

age ripple or load-transient response is required (see

Figure 2). To guarantee stability, it is recommended that

the phase margin be measured under the worst-case

deration of the output capacitor(s). Due to the soft-start

sequence, the PMICs are unable to drive arbitrarily large

output capacitors.

Thermal Considerations

How much power the package can dissipate strongly

depends on the mounting method of the IC to the PCB

and the copper area for cooling. Using the JEDEC test

standard, the maximum power dissipation allowed is

2285mW in the TQFN package. More power dissipation

can be handled by the package if great attention is given

during PCB layout. For example, using the top and bottom

copper as a heatsink and connecting the thermal vias to

one of the middle layers (GND) transfers the heat from the

package into the board more efficiently, resulting in lower

junction temperature at high power dissipation in some

PMIC applications. Furthermore, the solder mask around

the IC area on both top and bottom layers can be removed

to radiate the heat directly into the air. The maximum

allowable power dissipation in the IC is as follows:

(

)

J(MAX)

MAX

−

+ θ

where TJ(MAX) is the maximum junction temperature

(+150°C), TAistheambientairtemperature,θJC (3°C/W

for the 28-pin TQFN) is the thermal resistance from the

junctiontothecase,andθCA is the thermal resistance from

the case to the surrounding air through the PCB, copper

traces,andthepackagematerials.θCA is directly related

to system-level variables and can be modified to increase

the maximum power dissipation.

The TQFN package has an exposed thermal pad on its

underside. This pad provides a low thermal-resistance path

for heat transfer into the PCB. This low thermally resistive

path carries a majority of the heat away from the IC. The

PCB is effectively a heatsink for the IC. The exposed pad

should be connected to a large ground plane for proper

thermal and electrical performance. The minimum size

of the ground plane is dependent upon many system

variables. To create an efficient path, the exposed pad

should be soldered to a thermal landing, which is connected

to the ground plane by thermal vias. The thermal landing

should be at least as large as the exposed pad and can be

made larger depending on the amount of free space from

the exposed pad to the other pin landings. A sample layout

is available on the evaluation kit to speed designs.

PCB Layout Guidelines

Careful PCB layout is critical to achieve low switching

lossesandclean,stableoperation.Useamultilayerboard

whenever possible for better noise immunity and power

dissipation. Follow these guidelines for good PCB layout:

1) UsealargecontiguouscopperplaneunderthePMIC

packages. Ensure that all heat-dissipating components

have adequate cooling.

2) Keep the high-current paths short, especially at the

ground terminals. This practice is essential for stable,

jitter-free operation. The high current path comprising

of input capacitor, inductor, and the output capacitor

should be as short as possible.

3) Keep the power traces and load connections short. This

practiceisessentialforhighefficiency.Usethickcopper

PCBs (2oz vs. 1oz) to enhance full-load efficiency.

4) Use a single ground plane to reduce the chance of

ground potential differences. With a single ground

plane, enough isolation between analog return signals

and high-power signals must be maintained.

MAX20029/MAX20029B/

MAX20029C/MAX20029D

Automotive Quad/Triple Low-Voltage

Step-Down DC-DC Converters

www.maximintegrated.com

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